CERN
Author in the following contributions
- An Advanced Power Analysis Methodology Targeted to the Optimization of a Digital Pixel Readout Chip Design and its Critical Serial Powering System
- Radiation Hardened by Design, Low Jitter, 2.56 Gbps LVDS/SLVS Based Receiver in 65 nm CMOS
- Characterization of Radiation Effects in 65nm Digital Circuits with the DRAD Digital Radiation Test Chip
