21–25 Sept 2009
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France
Europe/Paris timezone
<strong>The deadline for paper submission has been extended to 23 October 2009</strong>

FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links

25 Sept 2009, 10:35
25m
Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Oral Programmable Logic, design tools and methods Plenary Session 6 - Programmable Logic, Boards, Crates and Systems

Speaker

Mr Csaba Soos (European Organization for Nuclear Research (CERN))

Description

Reliable optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Ratio (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in Xilinx FPGA devices and discusses the experimental results.

Summary

In the framework of the Versatile link project [1], optical transceiver components will be tested to verify their compliance with the requirements of future radiation hard optical links in High-Energy Physics experiments. A widely accepted method to test digital transmission systems and their components is the Bit-Error-Ratio (BER) test. In order to quantify the effects of radiation the components will be irradiated and the impact of the Single-Event Upsets (SEU) on the BER will be investigated.

Measuring the BER with high confidence level (> 0.95) is usually a lengthy process, thus testing components sequentially takes too much time. Therefore, a multi-channel BER Tester (BERT) supporting the measurement of several components simultaneously has been developed. The BERT operates at multiple data rates up to a maximum of 6.5 Gbit/s. Unlike standard equipment that uses pseudo-random bit patterns, the BERT described uses the custom physical layer protocol, which is proposed by the GigaBit Transceiver (GBT) project [2]. In order to cope with the radiation induced SEUs, the protocol will include Forward Error Correction (FEC). By measuring the BER both before and after the error correction, the tool can be used to evaluate the performance of the FEC in the radiation environment.

Detailed information about the architecture, the implementation in Xilinx Virtex-4 and Virtex-5 FPGA devices, as well as a procedure to improve the measurement time will be discussed in the paper. Results of laboratory BER tests of standard components will be shown for reference and finally results from the SEU tests will be presented.

Primary author

Mr Csaba Soos (European Organization for Nuclear Research (CERN))

Co-authors

Mr Christophe Sigaud (European Organization for Nuclear Research (CERN)) Mr Ioannis Papakonstantinou (European Organization for Nuclear Research (CERN)) Mr Jan Troska (European Organization for Nuclear Research (CERN)) Mr Paulo Moreira (European Organization for Nuclear Research (CERN)) Mr Pavel Stejskal (European Organization for Nuclear Research (CERN)) Mr Spyridon Papadopoulos (European Organization for Nuclear Research (CERN)) Mr Stéphane Detraz (European Organization for Nuclear Research (CERN)) Mr Sérgio Silva (European Organization for Nuclear Research (CERN))

Presentation materials