TWEPP-09 Topical Workshop on Electronics for Particle Physics

ASPIC: LSST camera readout chip Comparison between DSI and C&S

24 Sept 2009, 16:15

2h 15m

Institut des Cordeliers 15, rue de l'Ecole de Médecine (Métro Odéon) Paris, France

Poster ASIC's POSTERS SESSION

Speaker

Mr François WICEK (LAL IN2P3 CNRS)

Description

The ASPIC chip has been designed to readout the 3.2Gpixels of the LSST camera focal plane. The dynamic range is more than 16 bit and the noise has to be less than 7µV rms with a crosstalk better than 0.05%. The architecture is based on a double correlated sampling. 2 methods have been investigated: differential output Dual Slope Integrator which has been chosen to be the LSST baseline and Clamp and Sample. We plan to perform a deep comparison between these methods and therefore 2 ASICs have been designed in 5V compliant CMOS 0.35µm.

Summary

The LSST camera will have more than 3000 video-processing channels
to readout its large and highly segmented focal plane, requiring a compact readout chain.
The standard technique for analog signal processing of CCDs is “Correlated Double Sampling,” which can be implemented with “Dual Slope Integrator” or “Clamp and Sample” methods. We have designed and implemented an ASIC for LSST to directly compare the strengths and weaknesses of these methods on a working device: the Analog Signal Processing asIC (ASPIC). Four channels of each method have been implemented on the same ASIC to perform direct comparisons and fine crosstalk measurements.
Video channel to video channel crosstalk due to electronics (cables, boards, chips) has to be no more than 0.05% (1::2000) with a 0.01% goal (1::10000) at 500kHz readout frequency. The other requirements on this readout chain are:
- readout noise < 7µV rms for an integration time of 500ns
- crosstalk < 0.05%
- linearity < 1%
- dynamic range 16 bits
- maximum power consumption of 25mW/channel
- working temperature 173 K
- differential ouputs driving 1kΩ // 50pF load
The chosen technology is 5V compliant CMOS 0,35µ by AMS.

A second version, ASPIC 2, containing 8 DSI channels has been submitted by the end of 2008. This version is characterized by a 3 bit programmable gain (made by capacitive feedback) of the input amplifier, and a 3 bit programmable time constant integrator in order to match the CCD output conversion and the readout frequency. In order to reduce the power consumption, an idle mode has been implemented. First measurements show an important improvement in noise which has been reduced to less than 7µV for an integration time of 500ns at room temperature. Power consumption is now around 26mW/ch also at room temperature. A very preliminary crosstalk of 0.02% has been measured on a socket mounted chip.

A CLAmp and Sample aSIC (CLASSIC) chip containing 8 channels has been submitted in march in order to perform a comparison between the two methods. CLASSIC is also characterized by a programmable input amplifiers gain and a programmable time constant output filter.
Both ASPIC and CLASSIC will be readout with a specific Back End board containing eight 18 bits ADC channels which are the LSST Back End Board ADC, 256 kwords memory and an USB interface. This board will permit CDD correlated noise measurement.