Speaker
Description
Summary
We are developing Silicon-On-Insulator (SOI) pixel detector. While our fabricated SOI pixel detectors operate as we expected, at this moment a sufficient detector bias voltage can not be applied due to so called back gate effect. To overcome this, we have introduced two new techniques in the fabrication processes, based on TCAD simulations performed to understand the phenomenon in details.
SOI technology enables a monolithic pixel detector by bonding thick, high-resistivity semiconductor sensors and thin, low-resistivity readout electronics layer with insulating buried oxide layer (BOX). Contacts between the sensing nodes of the sensor layer and the readout circuitry are made through the BOX layer.
Compared to conventional bulk CMOS pixel sensors, SOI pixel sensor has following advantages:
* No mechanical bump bonding; minimizing multiple scattering in the detector and smaller pixel size is possible.
* Small parasitic capacitance (~10fF) of sensing nodes gives large conversion gain and lower noise.
* Small active volume in each transistor ensures latch-up immunity and high radiation tolerance.
* Both sensor and readout electronics can be fabricated with the industry standard SOI process; further progress and lower cost are expected.
While the SOI structure is ideal for realizing the monolithic pixel detector, applied electric field in the sensor layer also affects transistors in the adjacent LSI circuit layer (back gate effect). Due to this phenomenon, sufficient bias voltage to make the sensor full depletion can not be applied at this moment.
To overcome this, we made TCAD simulation to understand the phenomenon in detail. Based on these TCAD simulation study, we have tried two methods in the fabrication process.
First method is an introduction of a buried p-well (BPW) in the substrate. A p-type Dopant is implanted through the top Si layer and forms p-well just below the buried oxide (BOX) layer. This BPW region acts as a Faraday cage to shield the electric field from the Sensor layer and the transistors in the top LSI circuit layer may not be affected. The doping level of the BPW is about 3 orders lower than that of the p+ sensor node and drain/source region, so it does not affect the transistors in the top LSI circuit layer.
The other method is a 3D vertical integration technique. We will bond two SOI wafers face to face by using micro-bump technology of ZyCube Co. Ltd. Minimum pitch of the bump is 5um. This will not only enables higher circuit integration density but also will separate the sensitive circuit regions from the sensor.
We have developed a 0.2 um fully-depleted (FD) SOI pixel process in collaboration with OKI Semiconductor Co. Ltd. Additional processing steps to create BPW and contacts between sensor nodes and readout circuitry were established.
To reduce development cost, we have been organizing MPW (Multi Project wafer) runs. Two MPW runs were completed and one runs is now being processed. In each run, we have about 16 designs from our collaborators.
In this presentation, the techniques and preliminary results will be shown.
