Speaker
Description
Over the last years the ATLAS Pixel Detector has been upgraded in terms of sensors and readout electronics. The readout-driver cards have been upgraded for the entire Pixel Detectors, which features millions of channels to stand the on-going increment of luminosity of the collider at CERN. The challenge of upgrading the readout electronics for the huge matrices of pixel detectors has led us to design and fabricate a PCI_express board (Pixel-ROD) with all the necessary I/Os looking at the performance to interface with the current and future front end electronic chains. For example, the intention is to interface with the GBT and RD53A chips that will be used for the LHC upgrade.
In particular the GBTx communication has recently been optically interfaced at a rate of 10 Gb/s with a mini-FELIX card in the NIKHEF laboratory in Amsterdam. Other tests have been physically carried out at a rate of 4.8 GB/s using the 64b/66b Aurora protocol.
We are building a demonstrator tool able to emulate a data-taking of physical streams, by connecting together many Pixel-ROD boards. Also, an 8-hour PCI-express DMA readout has been proved towards a PC mother board, with an overall bit-error-rate less than 10^-15.
The Pixel-ROD board features a 8x PCI express bus and two Xilinx FPGAs: the Kintex7 XC7K325T-2FFG900C and the Zynq XC7Z020-1CLG484C with an embedded physical dual-core ARM Cortex-A9 processor. The Kintex device tested 16 transceivers nominally running at up to 12 Gs/s. These 16 GTx are connected to different types of physical ports: 8 PCI_express, 4 HPC FMC, 1 LPC FMC, 1 SMA, 1 SFP and 1 Gb-Ethernet port. So far we have proved the coaxial link to the SMA, the optical channel to the SFP and the Ethernet links up to 10 Gb/s.
In addition the two Xilinx devices feature DDR3 external memories tested with read-write cycles at 667 MHz.
The Pixel-ROD board can be equipped with a firmware derived from the one that is currently working into the BOC and ROD boards of the ATLAS Pixel Detector.
As the Pixel-ROD features 16 GTx channels we are proposing the board as a tool to test, qualify and read out the recent chips and/or channels under development to interface new generation of pixel detectors, besides those for the LHC upgrade. We are planning to extend the use of the board within other CERN-based collaborations.
