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Development of a cryogenic readout circuit based on FD-SOI CMOS for a far-infrared astronomical image sensor

10 Dec 2017, 20:33
1m
Conference Center (Okinawa Institute of Science and Technology Graduate University (OIST))

Conference Center

Okinawa Institute of Science and Technology Graduate University (OIST)

OIST, Onna, Okinawa 904-0495, Japan
POSTER ASICs POSTER

Speaker

Dr Koichi Nagase (Japan Aerospace Exploration Agency)

Description

We are developing an image sensor with sensitivity to far-infrared (IR) wavelengths ranging from 30 to 200 $\rm \mu m$ for astronomical observations. Our image sensor consists of a cryogenic readout integrated circuit (ROIC) and a semiconductor detector, such as germanium which is often used for a far-IR detector. The detector must be cooled down below 2 K to reduce thermal noise; the dark current of the detector is reduced to be below 5 fA. To achieve the detector noise limit, the input leak current of the ROIC should be lower than the detector dark current. The ROIC based on MOSFETs is advantageous to achieve such very low leak current.

However, conventional bulk-MOSFETs, in particular NMOS FETs, show degradation such as the kink effect and hysteresis in drain current at cryogenic temperatures. These anomalies are caused by instability of the potential distribution in the MOSFETs under a carrier freezeout condition. In contrast, MOSFETs fabricated by a fully depleted silicon-on-insulator (FD-SOI) CMOS process show stable characteristics at cryogenic temperatures. Due to very thin Si bodies and thus full depleted ones, FD-SOI MOSFETs have no neutral region where the anomalies by carrier freezeout may happen. We designed the ROIC using FD-SOI CMOS whose I-V curves are not almost affected by the kink effect and the hysteresis.

The ROIC for multiple detector pixels consists of trans-impedance amplifiers and a multiplexer for switching output lines. In recent works, we developed a capacitive trans-impedance amplifier (CTIA) based on FD-SOI CMOS for impedance transformation and current/voltage conversion and evaluated the performance at 4 K. We demonstrated that our CTIA works as designed and that the input leak current is $\rm < 1.4 \times 10^{-17}~A$. Those results meet our requirements on the CTIA. Moreover, we designed an analog CMOS switch and a shift-resistor for the signal-multiplexing. In this presentation, we will report the development status of the cryogenic ROIC.

Primary author

Dr Koichi Nagase (Japan Aerospace Exploration Agency)

Co-authors

Dr Takehiko Wada (Japan Aerospace Exploration Agency) Dr Yasuo Arai (High Energy Accelerator Research Organization) Dr Hirokazu Ikeda (Japan Aerospace Exploration Agency) Dr Shunsuke Baba (The University of Tokyo) Dr Toyoaki Suzuki (Nagoya University) Dr Morifumi Ohno (National Institute of Advanced Industrial Science and Technology) Mr Takahiro Ishimaru (Japan Aerospace Exploration Agency)

Presentation materials