Speaker
Description
Mixed signal on chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with a sufficient ruggedness against ionizing radiation and single event burn out.
We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the lateral shallow trench isolation (STI) of the MOS transistors was replaced by narrow junction isolation regions. For a significant increase of the NLDMOS SEB onset voltage a cascode arrangement consisting of an isolated NMOS (i NMOS) and NLDMOS was chosen. The floating NLDMOS source node of the cascode arrangement is always reverse biased what efficiently avoids the turning on of the parasitic bipolar transistor of the NLDMOS. The junction isolated i NMOS/NLDMOS cascode features a break down voltage BVDS > 45V a maximum cut off frequency fT = 5 GHz and a maximum oscillation frequency fMAX = 14 GHz. In comparison with standard NLDMOS the laterally junction isolated i-NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.
