11th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors (HSTD11) in conjunction with 2nd Workshop on SOI Pixel Detectors (SOIPIX2017) at OIST, Okinawa, Japan

A Track Finder with Associative Memories and FPGAs for the L1 Trigger of the CMS experiment at HL-LHC

10 Dec 2017, 20:36

1m

Conference Center (Okinawa Institute of Science and Technology Graduate University (OIST))

POSTER ASICs POSTER

Speaker

Roberto Rossin (Universita e INFN, Padova (IT))

Description

The LHC accelerator at CERN is scheduled for an upgrade that will more than triple its instantaneous luminosity over the next decade. The Compact Muon Solenoid (CMS) experiment will have to cope with these new running conditions. The new tracking system under development will be capable of measuring the transverse momentum of charged particles down to 2-3 GeV/c at each bunch crossing (40 MHz), allowing for a Level-1 trigger decision that includes the precise tracking information. For this purpose, an architecture based on Associative Memories and FPGAs has been developed to identify hits and fit them into tracks in an overall processing latency of less than 4us. A hardware demonstrator system, based on a ATCA architecture, has been implemented to prove the feasibility of this approach and to measure its performances. We present the simulation/emulation framework utilized for the system optimization and the results from the hardware demonstrator.