Speaker
Description
SALT is a 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It
will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial
output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analogue
front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. The first version
of full 128-channel prototype was already tested and the second version was submitted. The design and tests
results will be presented.
Summary
Present Large Hadron Collider beauty (LHCb) detector performance is limited by readout electronics and data acquisition architecture. After the upgrade of LHC machine it will be capable to deliver more than one order of magnitude higher luminosity than presently used by the LHCb detector. To achieve this goal various detectors will need a new faster front-end electronics with the read-out running at the bunch-crossing rate of 40 MHz.
Silicon strip detectors in the upgraded Upstream Tracker (UT) of LHCb experiment will be read read out
by new Application Specific Integrated Circuit (ASIC) called SALT (Silicon ASIC for LHCb Tracking).
This 128-channel chip, designed in CMOS 130 nm technology, extracts and digitises analogue signals from the sensor,
performs Digital Signal Processing (DSP) and transmits a serial output data. The ASIC uses a novel architecture comprising an analogue front-end and an ultra-low power
($<$0.5~mW) fast (40~MSps) sampling 6-bit ADC in each channel. The front-end comprises a charge preamplifier
and a fast ($T_{peak}$=25ns and fast recovery) non-standard shaper with complex poles and zeros in transfer
function, required to distinguish between the LHC bunch crossings at 40~MHz. The front-end should work with
sensor capacitances between 5--20~pF. An ultra-low power ($<$1~mW) DLL is used to control precisely the ADC
sampling phase.
Digitised data from each ADC channel are processed in a DSP block which first subtracts pedestals and calculates mean common mode,
subtracted then in each channel. The last DSP step is zero suppression (ZS). After ZS the data are buffered in SRAM, then a packet is formed and sent to DAQ via a number of serial DDR e-links.
An ultra-low power ($<$1~mW) PLL is used in data serialization and fast data transmission circuitry.
An 8-channel prototype of the SALT, comprising most important functionalities, was designed,
fabricated, successfully tested and the results were already presented (TWEPP 2016).
The present 128-channel prototype is a complete ASIC for LHCb detector.
It includes, except functionalities mentioned above, internal
generation of common mode voltage, monitoring ADCs (for PLL, DLL and internal DACs), band-gap reference
source, variable number of active e-links, hybrid suitable power distribution, etc..
The 128-channel SALT prototype was tested and found functional. In the first step, the digital
functionality and operation were extensively tested (serializers and deserializer with DDR e-links, the DSP
operations, fast and slow control interfaces, etc.) and, except several small features, all functionalities
were correct. After verification of digital processing and data transmission analogue pulses were observed,
using DLL to shift the ADC sampling phase. The ADC performance fully agrees with expectations.
The analogue front-end measurements qualitatively agreed with simulations, although quantitative
results on noise and mismatch between channels showed that improvements in the design are still needed.
The results of tests with discussion of possible improvements and planned corrections will be
presented.
