TWEPP 2017 Topical Workshop on Electronics for Particle Physics

UC Santa Cruz SCIPP 1156 High St Santa Cruz, CA 95064
Alessandro Marchioro (CERN), Alex Grillo (University of California,Santa Cruz (US))

The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

Official Web site for local information and registration

The purpose of the workshop is :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities
- to review the status of electronics for the LHC experiments
- to identify and encourage common efforts for the development of electronics
- to promote information exchange and collaboration in the relevant engineering and physics communities.

Registration to the workshop and local organisation information are available on:

Organised by SCIPP (Santa Cruz Institute for Particle Physics) with support from CERN.

Evaluation of TWEPP 2017
    • Opening and Welcome Earth and Marine Sciences (E&MS) Building, UCSC

      Earth and Marine Sciences (E&MS) Building, UCSC

      Conveners: Alessandro Marchioro (CERN), Alex Grillo (University of California,Santa Cruz (US))
    • 9:50 AM
      Coffee Break
    • Invited Talk Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) Building
      Convener: Alex Grillo (University of California,Santa Cruz (US))
      • 3
        Welcome to SCIPP - Research at SCIPP and at UCSC Earth and Marine Sciences (E&MS) Building

        Earth and Marine Sciences (E&MS) Building

        Earth and Marine Sciences (E&MS) Building
        Speaker: Prof. Jason Nielsen
      • 4
        Neuron detectors: electrical and optical interactions with neural networks. Earth and Marine Science (E&MS) Building (UCSC)

        Earth and Marine Science (E&MS) Building


        Neurons in the brain interact with each other through electrical and chemical signals. These interactions determine how the brain detects and processes information. Simultaneous detection of the activity of many neurons is crucial for understanding the brain function. I will describe electrical and optical methods of interacting with neural networks developed with SCIPP’s participation. I will also discuss some of the neuroscience findings obtained obtained with the developed methods.

        Speaker: Prof. Alexander Sher (UCSC)
    • 1:00 PM
      Lunch Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
    • Invited Talk Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Earth and Marine Sciences (E&MS) Building
      Convener: Philippe Farthouat (CERN)
      • 5
        LCLS-II: A High Repetition Rate X-Ray Laser Facility

        The Linac Coherent Light Source (LCLS) is in the midst of a major upgrade called LCLS-II [1]. This upgrade will add a 4 GeV continuous-wave superconducting electron accelerator to the LCLS complex, delivering a 10,000-fold increase in repetition rate and average x-ray brightness. Currently scheduled to achieve first light in 2020, LCLS-II will enable a broad range of experiments over a 0.2 to 5 keV photon energy range presently not possible to date [2]. These experiments will be conducted in three newly developed x-ray instruments. The scope, projected capabilities and status of the LCLS-II project and associated x-ray instruments will be presented as well as exemplary science applications.

        [1] J. N. Galayda, Proceedings of the 5th International Particle Accelerator Conference (IPAC’14), 15-20 June 2014, Dresden, Germany
        [2] New Science Opportunities Enabled by LCLS-II X-ray Lasers, SLAC-R-1053 [2015],

        Speaker: David M. Fritz (SLAC National Accelerator Laboratory)
    • Radiation Tolerant Components and Systems Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Earth and Marine Sciences (E&MS) building
      Convener: Salvatore Danzeca (CERN)
      • 6
        Radiation Hardness Studies and Evaluation on SRAM-Based FPGA for High Energy Physics Experiments

        Being a proposed solution for the digital boards of the upgraded LHCb RICH sub-detectors, SRAM-based FPGA devices have become widely used in high energy physics experiments. These studies aim to present the radiation hardness measurements done on the KINTEX-7 FPGA during irradiation with protons, X-rays and ions beams. For multiple values of the total ionising dose, linear energy transfer and proton energy, the cross sections of single-event-effects are estimated. We also give separate results for specific resources type: configuration RAM, block RAM, I/O banks and logic. Conclusions are reached on the radiation tolerance of this chip family in LHC environment.

        Speaker: Vlad-Mihai PLACINTA (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH) & Polytechnic University of Bucharest)
      • 7
        Effect of Gamma Irradiation on Leakage Current in CMOS Readout Chips for the ATLAS Upgrade Silicon Strip Tracker at the HL-LHC

        As part of the program for the upgrade of the ATLAS inner tracker for the High Luminosity LHC, irradiations have been carried out with 60Co gamma source. The measurements characterize the increase in the leakage current in the 130 nm-technology readout chips. The current as a function of total ionizing dose has been studied under different conditions: dose rate, temperature, power applied to the chip and pre-irradiation. The results show unique features that provide valuable information for the understanding of the mechanisms responsible for radiation damage in transistors. Models that attempt to parameterize the leakage current will also be presented.

        Speaker: Stefania Antonia Stucci (Brookhaven National Laboratory (US))
      • 8
        A SEU Tolerant Latches Study for the RD53A Chip

        The RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process is adopted in order to satisfy the high level of integration requirement. The SEU immunity for this highly scaled process should be carefully considered because the device dimensions are small and the capacitance of the storage nodes becomes very low.
        A chip prototype including different SEU tolerant structures was designed in the TSMC 65nm technology and proton irradiation tests were done in order to estimate the SEU tolerance of the proposed structures.

        Speaker: Denis Fougeron (Centre National de la Recherche Scientifique (FR))
    • Trigger Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Thimann I Lecture Hall
      Convener: Philippe Farthouat (CERN)
      • 9
        An FPGA-Based Track Finder for the L1 Trigger of the CMS Experiment at HL-LHC

        A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC. This upgrade will allow to reconstruct within a few microseconds charged particle tracks with transverse momentum above 3 GeV, for use in the Level-1 trigger. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, reconstructing tracks using an Hough Transform based algorithm. A hardware demonstrator using MP7 boards has been assembled. It operates on 1/8 of tracker solid angle at a time, processing events taken at 40 MHz with up to 200 superimposed proton-proton interactions, satisfying latency constraints.

        Speaker: Davide Cieri (STFC - Rutherford Appleton Lab. (GB))
      • 10
        The ATLAS Muon-to-Central Trigger Processor Interface for the Phase-I Muon Trigger Upgrade

        The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at CERN will be upgraded for run 3 of the LHC. The current system, a full 9U VME crate, will be replaced by a single AdvancedTCA blade, based on state-of-the-art FPGA technology and high-density ribbon fibre-optic transmitters and receivers. The module uses a System-on-Chip (SoC) with a processor running an embedded Linux operating system to communicate with the experiment run control system. We present the hardware design and implementation of the module, the communication model used in the SoC as well as results from the validation of the first prototype.

        Speaker: Paschalis Vichoudis (CERN)
      • 11
        Development of the jet Feature EXtractor (jFEX) for the ATLAS Level 1 Calorimeter Trigger upgrade at the LHC

        To cope with the enhanced luminosity delivered by the Large Hadron Collider in 2021, the ATLAS experiment has planned a major upgrade. The first level trigger based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (FEXs), each optimized to trigger on different physics objects. This presentation is focused on the jet FEX.
        The main challenges of such a board are the input bandwidth of up to 3 Tb/s, dense routing of high-speed signals and power consumption. We report on design, firmware development and results of integrated tests of a prototype.

        Speaker: Marcel Weirich (Johannes Gutenberg Universitaet Mainz (DE))
    • 4:05 PM
      Coffee break
    • ASIC Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Earth and Marine Sciences (E&MS) building
      Convener: Christophe De La Taille (OMEGA (FR))
      • 12
        CBC3: a CMS Micro-Strip Readout ASIC with Logic for Track-Trigger Modules at HL-LHC

        The CBC3 is the latest version of the CMS Binary Chip for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon micro-strip sensors with aligned micro-strips. On-chip logic identifies L1 trigger primitives from high transverse-momentum tracks by selecting correlated hits in the sensors. Delivered in late 2016, the CBC3 has been under test for several months, including x-ray irradiations and SEU testing. Results and performance are reported.

        Speaker: Mark Prydderch (STFC Rutherford Appleton Laboratory)
      • 13
        A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links

        This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL–LHC experiments. The PLL features a novel LC-oscillator architecture which is 600× less sensitive than traditional structures. Additionally, the circuit uses triple-modular redundancy and is designed in 65nm CMOS. The paper will present experimental results on X-ray Total Ionizing Dose (TID), heavy ion SEU and two-photon absorption laser tests.

        Speaker: Jeffrey Prinzie (KU Leuven (BE))
      • 14
        Characterization of a 9-Decade Femtoampere ASIC Front-End for Radiation Monitoring

        An ultra-low current sensing digitizer circuit for radiation monitoring for personnel and environmental safety was designed.
        The ASIC includes some key functionalities like on-chip active leakage current compensation and multi-range charge balancing. The calibration procedure and the measurements of the Ultralow Picoammeter 2 (Utopia 2) ASIC are presented. This chip can measure input current over a wide dynamic range of 9 decades starting from a few femtoamperes. The ASIC has been characterized for its ultra-low current performance in the Swiss Federal Institute of Metrology. Radiation measurements when the front-end was connected to the ionization chambers used at CERN are presented.

        Speaker: Evgenia Voulgari (CERN)
      • 15
        An 8-Channel ASD in 130 nm CMOS with Superior Performance of Rise Time, Noise and Threshold Uniformity for ATLAS Drift Tube Readout at the HL-LHC

        ATLAS Muon-Drift-Tubes spatial resolution-&-efficiency depend on drift-time resolution, noise levels, and accurate threshold setting. A new 130nm read-out device is developed and optimized, for the required time resolution, to guarantee rise-times below 10ns, with acceptable time-slewing effects. Moreover, the large chain-amplification results in increased sensitivity to any disturbance (mainly from supply). To avoid additional costs to clean up the set-up from such disturbs, the read-out chain adopts innovative techniques (at system, circuit, and design levels) minimizing read-out chain disturb sensitivity. This paper details the design strategy, compares post-layout simulation with measurements and presents resolution studies in CERN high-energy testbeam.

        Speaker: Markus Fras (Max-Planck-Institut fur Physik (DE))
    • Systems, Planning, Installation, Commissioning and Running Experience Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Thimann I Lecture Hall
      Convener: Julie Whitmore (Fermi National Accelerator Lab. (US))
      • 16
        Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

        The present small wheel muon detector at ATLAS will be replaced with a New Small Wheel (NSW) detector to handle the expected rate at the increase in data rates and harsh radiation environment expected at the LHC. Resistive Micromegas and small-strip Think Gap Chambers will be used to provide both trigger and tracking primitives. A new trigger and readout system is developed for the NSW detector. The new system has about 2.4 million trigger and readout channels and about 8,000 frontend boards. We will discuss the overall electronics design and studies with various ASIC and board prototypes.

        Speaker: Xueye Hu (Umich)
      • 17
        NEBULA Large Band Digitiser for Radio Astronomy

        NEBuLA is a large band autonomous digitiser under development, with use cases in radio astronomy.
        We present the scientific rationale and the specifications of the project, We describe the board overall architecture,
        the implementation of the different links: synchronisation, command, control and data transfer. We present
        the solution adopted to fulfil the main requirement of the project which is the possibility to synchronise
        the clocks of multiple boards separated by distances up to several km. Finally, we present the firmware
        and the software that we have developed for debugging, control and configuration and data transfer.

        Speaker: Daniel Charlet
      • 18
        A Data Acquisition System for the CLIC Vertex Detector Readout Chip.

        The DAQ of the CLICpix2 readout chip is based on the Control And Readout Inner tracking BOard (CaRIBOu). CaRIBOu is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. We present the design of the system and show examples of the achieved functionality and performance.

        Speaker: Adrian Fiergolski (CERN)
      • 19
        Design and Results from a Front-End Board for Micromegas Chambers in the ATLAS New Small Wheel

        The design and implementation of demonstrator front-end electronics for Micromegas detectors to be employed in the New Small Wheel, an ATLAS muon spectrometer upgrade, are presented. The demonstrator has 512 Micromegas detector channels as input. Signal processing and digitization utilize a custom ASIC developed by Brookhaven National Lab. Configuration, control and Ethernet readout functions are performed using an Artix-7 FPGA. Design constraints and considerations are discussed. Measurements of noise performance, both off- and on-detector, are presented. Results using an Fe-55 source are also shown. Design considerations for the final front-end electronics to be used in the ATLAS experiment are discussed.

        Speaker: Garrett Joseph Scott (University of Arizona (US))
    • 6:10 PM
      Welcome Reception Seymour Marine Discovery Center (Santta Cruz)

      Seymour Marine Discovery Center

      Santta Cruz

      Seymour Marine Discovery Center
    • Production, Testing and Reliability Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Thimann I lecture hall
      Convener: Alex Grillo (University of California,Santa Cruz (US))
      • 20
        The Development of Front-End Readout Electronics for ProtoDUNE-SP LAr TPC

        As a prototype of DUNE far detector, ProtoDUNE-SP single phase LAr TPC will sit in H4 beam line at CERN to study detector response to particles. It consists of 6 full-size APAs plus 2 CPAs, with total 15,360 TPC readout channels. The front-end readout electronics is comprised of cold electronics and warm interface electronics. The integral design concept of APA, cold electronics, feed-through, plus warm interface electronics with local diagnostic and strict isolation and grounding rules has been followed and studied at BNL. The production front-end readout electronics are being fabricated and will be installed in ProtoDUNE-SP in fall 2017.

        Speaker: Shanshan Gao (Brookhaven National Laboratory)
      • 21
        Quality Control Considerations for the Development of the Front End Hybrid Circuits for the CMS Outer Tracker Upgrade

        The upgrade of the CMS Outer Tracker for the HL-LHC requires the design of new double-sensor modules. They contain two high-density front end hybrid circuits, equipped with flip-chip ASICs, passives and mechanical structures. First prototype hybrids in a close-to-final form have been received from three manufacturers. To qualify these hybrids a test setup was built, which emulates future tracker temperature and humidity conditions, provides temporary interconnection, and implements testing features. The system was automated to minimize the testing time in view for the production phase. Failure modes, deliberately implemented in the produced hybrids, provided feedback on the system’s effectiveness.

        Speaker: Tomasz Gadek (CERN)
      • 22
        Functional Tests of 2S Modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-Based Readout System

        First full size 2S module prototypes for the CMS Phase-2 Tracker Upgrade have been assembled. With two sensors with realistic geometries and 16 CBC2 readout chips on two front-end hybrids, the characteristics of these complex objects can be studied.
        A microTCA based readout system was developed to test multiple front-end hybrids simultaneously. Therefore the concurrent information of the full module can be used for differential and common-mode noise characterization, as well as for signal tests with radioactive sources or cosmic particles.
        This talk will discuss the readout system and test results obtained with the first full size 2S module prototypes.

        Speaker: Marius Preuten (Rheinisch-Westfaelische Tech. Hoch. (DE))
    • Programmable Logic, Design Tools and Methods Earth and Marine Sciences (E&MS) building (UCSC)

      Earth and Marine Sciences (E&MS) building


      Earth and Marine Sciences (E&MS) Building
      Convener: Magnus Hansen (CERN)
      • 23
        SEE Tolerant Standard Cell Based Design While Guaranteeing Specific Distance Between Memory Elements

        Single Event Effects (SEEs) comprising of Single Event Upsets (SEUs) and Single Event Transients (SETs) corrupts the data in storage nodes/registers. Triple Modular redundancy (TMR) with clock delay insertion is a system level technique that counters SEEs in storage nodes. However, such an implementation is not straight forward in standard cell based digital design which uses cad tools like Genus/RC compiler and Innovus for synthesis & Physical design. This paper presents a successful automation methodology that maps the intended registers in the Verilog RTL with triplicated cell during synthesis and guarantees minimum distance between memory elements during placement & routing leading to SEE tolerant standard cell based digital design.

        Speaker: Sandeep Miryala (Fermi National Accelerator Lab. (US))
      • 24
        Clock and Trigger Distribution for ALICE Using the CRU FPGA Card

        ALICE is preparing a major upgrade for 2021.

        Subdetectors upgrading their counting room DAQ electronics will use a
        common hardware to receive physics data: the Common Readout Unit (CRU).
        The same CRU will also distribute the LHC clock and trigger to many of
        the upgrading subdetectors (~7800 front end cards).

        Requirements are strict: for the clock the allowed jitter (RMS) is
        typically <300ps, and <30ps for timing critical subdetectors; the
        allowed skew is typically <1ns, and <100ps for timing critical
        subdetectors. A constant latency for distributing the trigger is a

        Techniques used to meet these requirements will be presented.

        Speaker: Jozsef Imrek (Hungarian Academy of Sciences (HU))
      • 25
        DRM2: the Readout Board for the ALICE TOF Upgrade

        For the upgrade of the ALICE TOF electronics, we have designed a new version of the readout board, named DRM2, a card able to read the data coming from the TDC Readout Module boards via VME. A Microsemi Igloo2 FPGA acts as the VME master and interfaces the GBTx link for transmitting data and receiving triggers and a low- jitter clock. Compared to the old board, the DRM2 is able to cope with faster trigger rates and provides a larger data bandwidth towards the DAQ. The measurements on the received clock jitter and data transmission performances in a full crate are given.

        Speaker: Davide Falchieri (Universita e INFN, Bologna (IT))
    • 9:46 AM
      Coffee break
    • Invited Talk Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Earth and Marine Sciences (E&MS) Building
      Convener: Alessandro Marchioro (CERN)
      • 26
        Advances in Image Sensors Technologies

        Image sensor innovation continues after more than 50 years of development. New image sensor markets are being developed while old markets continue to grow. Higher performance and lower cost image sensors are enabling these new applications. Although CMOS image sensors dominate the market, CCDs and other novel image sensors continue to be developed. In this talk we discuss trends in image sensor technology and present results from selected workshop papers. Moreover, we will discuss developments in small pixels, stacked die image sensors, time of flight image sensors, SPAD image sensors, low light level sensors, wide dynamic range sensors and global shutter image sensors.

        Speaker: Dr Boyd Fowler (Omnivision)
    • ASIC Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Earth & Marine Sciences (E&MS) Building
      Convener: Angelo Rivetti (Universita e INFN Torino (IT))
      • 27
        Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Pixel Upgrades

        The development of a large scale 65nm CMOS pixel demonstrator chip for very high rate (3GHz/cm2) and very high radiation levels (1Grad) for ATLAS and CMS phase 2 pixel upgrades has taken place within the RD53 collaboration. The development and testing of radiation test structures, building blocks and small scale pixel array demonstrators are summarized together with test and radiation characterization results. The design and verification of a large scale (20mm x 12mm) pixel chip demonstrator, RD53A is described together with an outline of the plans to develop final pixel chips for the two experiments.

        Speaker: Elia Conti (CERN)
      • 28
        ALTIROC0, a 20 Pico-Second Time Resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

        ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS HGTD detector. The targeted combined time resolution of the sensor and the readout electronics is 30 ps/MIP. Each analog channel of the ASIC must exhibit an extremely low jitter noise to ensure this challenging time resolution, while keeping a low power consumption of 2 mW/channel. A “Time Over Threshold” and a “Constant Fraction Discriminator” architecture are integrated to correct for the time walk.
        The ASIC was received in April 2017 and testbench measurements will be presented.

        Speaker: Christophe De La Taille (OMEGA (FR))
      • 29
        A 2 Gsps Waveform Digitizer ASIC in CMOS 180 nm Technology

        The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a sampling rate of 2 Gsps with an analogue -3 dB bandwidth of more than 400 MHz. Each channel integrates 128 sampling cells and a ramp-compare ADC. With this ASIC, sine waveform and reconstructed PMT waveform recording tests were conducted. We also evaluated its performance on fast pulse timing, and the timing precision is proved to be better than 20 ps RMS after a series of correction strategies.

        Speaker: Dr Jiajun Qin (State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China Department of Modern Physics, University of Science and Technology of China)
      • 30
        MuTRiG: A Silicon Photomultiplier Readout ASIC with High Timing Precision and High Event Rate Capability

        The MuTRiG chip, which is dedicated to the Mu3e experiment, is a 32 channel
        mixed-signal Silicon Photomultiplier readout ASIC with high timing precision
        and high event rate capability designed and fabricated in UMC 180 nm CMOS
        technology. It combines the excellent timing performance of the fully
        differential analog front-ends and the 50 ps time binning TDCs with a high
        event rate capability from a dedicated on-chip digital logic circuit and a
        gigabit LVDS serial data link. The design of the chip and the results from the
        characterization measurements will be presented.

        Speaker: David Schimansky (Heidelberg University)
    • Systems, Planning, Installation, Commissioning and Running Experience Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Thimann I Lecture Hall
      Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
      • 31
        Commissioning and First Running Experiences with the TOP Barrel PID Detector in the Belle II Experiment

        The Time of Propagation (TOP) detector is a novel Cherenkov barrel particle identification system built for the Belle II detector upgrade based on quartz radiator bars read out by Micro-Channel Plate PMTs. The readout electronics of the TOP system are built around a switched capacitor array waveform sampling ASIC operating at 2.7GSa/s. Acquired waveforms are processed in real time in the front end electronics, extracting the individual timing of detected photons to better than 100ps.

        This talk presents the current status of commissioning, calibration and operation of the Belle II TOP detector.

        Speaker: Oskar Hartbrich (University of Hawaii at Manoa)
      • 32
        Validation of the Front-End Electronics and Firmware for LHCb Vertex Locator.

        The LHCb Experiment will be upgraded to a trigger-less system reading out the full detector at 40
        MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator
        (VELO) will be a hybrid pixel detector read out by the "VeloPix" ASIC with on-chip zero-suppression.
        This talk will present the systems overview and design of the VELO on-detector electronics and
        readout firmware. Results will show the evaluation of the prototypes boards and readout firmware.

        Speaker: Antonio Fernandez Prieto (Universidade de Santiago de Compostela (ES))
      • 33
        Upgrade of the ATLAS Thin Gap Chamber Electronics for HL-LHC

        The High-Luminosity LHC (HL-LHC) is planned to start the operation in 2026 with an instantaneous luminosity of 7.5 x 1034 cm-2s-1. To cope with the event rate higher than that of LHC, the trigger and readout electronics of ATLAS Thin Gap Chamber will be replaced and an advanced muon trigger with fast tracking will be implemented. A frontend board prototype was developed and the functions for HL-LHC including the data transfer of 256 channels with a 16 Gbps bandwidth have been demonstrated. A study on the fast tracking shows the rate reduction for a first-level single muon trigger by 30%.

        Speaker: Yasuyuki Horii (Nagoya University (JP))
      • 34
        CMS DAQ Current and Future Hardware Upgrades up to Post Long Shutdown 3 (LS3) Times

        Following the first LHC collisions seen and recorded by CMS in 2009, the DAQ hardware went through a major upgrade during LS1 (2013-2014) and new detectors have been connected during the 2016-2017 winter shutdown. Now, LS2 (2019-2020) and LS3 (2024-mid 2026) are actively prepared. This paper shows how CMS DAQ hardware has evolved from the beginning and will continue to evolve in order to meet the future challenges posed by High Luminosity LHC (HL-LHC) and the CMS detector evolution. In particular, post LS3 DAQ architectures are focused upon.

        Speaker: Attila Racz (CERN)
    • 1:00 PM
      Lunch Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
    • Invited Talk Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Earth and Marine Sciences (E&MS) Building
      Convener: Salvatore Danzeca (CERN)
    • ASIC Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Earth & Marine Sciences (E&MS) Building
      Convener: Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
      • 36
        The SALT, a 128-Channel Readout ASIC for Upstream Tracker in the Upgraded LHCb Experiment

        SALT is a 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It
        will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial
        output data. SALT is designed in CMOS 130~nm process and uses a novel architecture comprising of analogue
        front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. The first version
        of full 128-channel prototype was already tested and the second version was submitted. The design and tests
        results will be presented.

        Speaker: Krzysztof Piotr Swientek (AGH University of Science and Technology (PL))
      • 37
        Test Vehicles for CMS HGCAL Readout ASIC

        For the HGCAL calorimeter upgrade of CMS, two test vehicles were submitted in 2016. They provide the main building blocks of the future ASIC that will read out 50 pF Si-sensors over 10 pC dynamic range. The first test-vehicle features several variants of low-noise, dual-input-polarity current-sensitive preamplifiers. The second test vehicle has eight channels of the full analog-chain : preamplifiers, single-to-differential 25 ns shapers and 11-bit 40MHz SAR-ADC for charge measurement up to 100 fC. A fast discriminator and 50 ps TDC provide Time Over Threshold measurement up to 10 pC as well as Time of Arrival.
        Design and measurements of both chips realized in CMOS 130nm will be presented.

        Speaker: Damien Thienpont (IN2P3/OMEGA)
      • 38
        Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

        CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 $\mu m^2$. It is fully functional, can work at low thresholds down to 250e$^-$ and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented.

        Speaker: Luca Pacher (Universita e INFN Torino (IT))
    • Trigger Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Thimann I Lecture Hall
      Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
      • 39
        FELIX: the New Detector Readout System for the ATLAS Experiment

        Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

        Speaker: Frans Philip Schreuder (Nikhef National institute for subatomic physics (NL))
      • 40
        A High Luminosity LHC Track Trigger for the CMS Detector

        During the High Luminosity LHC, to maintain a managable trigger rate and achieve its physics goals,the CMS detector will need charged particle tracking at the hardware trigger level. The tracklet approach is a track-finding algorithm based on a road-search algorithm that has been implemented on commercially available FPGA technology. This algorithm has achieved high performance in track-finding and completes tracking within 3.4 \mus on a Xilinx Virtex-7 FPGA. An overview of the algorithm and its implementation on an FPGA are discussed and the results of an end-to-end demonstrator system that meets timing and performance requirements are presented.

        Speaker: Prof. Brian Winer (The Ohio State University)
      • 41
        Development of a High-Throughput Tracking Processor on FPGA Boards

        We present the latest results on the prototype of a tracking processor capable of reconstructing events in a silicon-strip tracker at about 40 MHz event rate with sub-microsecond latency. The processor is based on an advanced pattern-recognition algorithm, called “artificial retina”, inspired to the vision system of the mammals. We design and implement this processor on a board equipped with Altera Stratix V FPGA’s. Future applications of this novel approach as real-time track trigger at LHC experiments are also discussed.

        Speaker: Riccardo Cenci (SNS and INFN-Pisa, Italy)
    • 4:05 PM
      Coffee break
    • POSTER Session: 1 - ASIC Porter College Dining Hal (UCSC)

      Porter College Dining Hal


      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 42
        ALICE SAMPA-ASIC Second-Prototype Qualification Studies for LHC Run 3 and Beyond

        The ALICE experiment at the LHC plans an upgrade of its TPC, due to the expected high Pb-Pb collision-rate after the shutdown of LHC in 2018. In the upgraded TPC, Gas Electron Multiplier (GEM) chambers and continuous readout system will replace MWPC chambers and conventional triggered readout, respectively. In the continuous readout, GEM signals will be processed using 32 channels of SAMPA ASIC (preamplifier and ADC). The SAMPA second-prototype was delivered in 2016 and the production of the final version is in progress. During the presentation, test results of the SAMPA coupled with GEM detector prototype will be presented.

        Speaker: Dr Ganesh Jagannath Tambave (University of Bergen (NO))
      • 43
        Low Jitter, Radiation Hardened by Design, 2.56 Gbps LVDS/SLVS Based Receiver for Analog Time Transmission

        This paper proposes a novel 2.56 Gbps radiation hardened by design LVDS/SLVS like receiver for use in transmission systems requiring timing accuracy. The circuit, designed in a commercial 65 nm CMOS technology, uses a replica receiver with charge pump feedback. This feedback loop equalizes the propagation delay of the outputs rising and falling edge, independent of total ionizing dose (TID) radiation effects. The measured output signal has an RMS jitter of 3 ps at a maximum data rate of 2.56 Gbps. The circuit consumes only 1 mW of power from a 1.2 V power supply.

        Speaker: Mr Bram Faes (KU Leuven (BE))
      • 44
        Multi-Gigabit Wireless Data Transfer for High Energy Physics Applications

        The future of connectivity is wireless, and the HEP community is not an exception. The demand for high capacity data transfer continues to increase every year at a significant rate. For example the tracking detectors require readout systems with several thousand links that has to handle a data transfer of multiple-gigabit/s each. We propose to use the millimeter-wave band between (57-66 GHz). This 9 GHz band is very attractive in order to achieve high data transfer rate.
        This talk present current development of the 60 GHz transceiver chip for HEP applications. Studies of antenna and data transmission will be shown.

        Speaker: Mr Hans Kristian Soltveit (University of Heidelberg, Germany)
      • 45
        A Full Custom ASIC for Large Area 4-Dimensional Tracking

        Large area silicon trackers with excellent time and position resolution are now considered in the upgrade programs of the ATLAS and CMS detectors.

        In this contribution we present the development of a custom ASIC chip meant to be bump-bonded to segmented Ultra-Fast Silicon Detector, aiming to achieve a combined time resolution of $\sigma \sim$ 30 ps.

        The ASIC is implemented in standard CMOS 110 nm technology.

        Speaker: Nicolo Cartiglia (INFN Torino (IT))
      • 46
        ASICs and Readout System for a High Resolution UV Single Photon Imagining Detector

        Large aperture MCP based UV single photon imaging detectors are commonly used in space applications. NASA granted,the development of new detector with a geometrical acceptance up to a 100x100 mm, as well as ASICs for the construction its readout system. We developed the detector and ASIC chips which enabled the construction of it's readout system. The system is composed of fast, low noise and low power 16ch CSA amplifier ASICs, and 16ch waveform sampling GSPS ASICs. The detector and readout system are currently under evaluation, meanwhile a novel and even more compact readout system on chip is undergoing design process.

        Speaker: Dr Andrej Seljak (UH Hawai'i Manoa )
      • 48
        A 4-Channel Parallel 56 Gb/s CMOS Optical Receiver for VCSEL-Based Optical Links

        A 4-channel parallel 56 Gb/s optical receiver for VCSEL-based optical links is presented. The receiver has been manufactured in a standard 65nm-CMOS process. Simulation results with layout parasites and a model of a wire-bonded photo diode demonstrate that the single channel works at bit rate of 14 Gb/s and has an input sensitivity of better than 20 uApp, an input-referred noise of 2.3 uArms and a differential output amplitude across an external 50 ohm load of larger than 400 mVpp. The power consumption is 84 mW/channel for a power supply of 1.2 V. Test results will also be presented in the conference.

        Speaker: Dr Chaosong Gao (Department of Physics, Central China Normal University, Wuhan, Hubei 430079, P.R. China)
      • 49
        A 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector Upgrade at HL-LHC

        The MPA is the pixel readout ASIC for the hybrid Pixel-Strip module of the Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It employs a novel technique for identifying high transverse momentum particles and provides this information at a 40$\,$MHz rate to the L1-trigger system. The chip also comprises a binary pipeline buffer for the L1-trigger latency, and a data path to support the readout of full events with a maximum trigger rate of 1$\,$MHz and a latency of 12.8$\,\mu$s. The design and implementation in a 65$\,$nm CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation are presented in this contribution.

        Speaker: Davide Ceresa (CERN)
      • 50
        A Digital Processing Unit of a Highly Integrated Receiver Chip for PMTs in JUNO

        The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment based on a 20,000 ton liquid scintillator with the one main objective to determine the neutrino mass hierarchy. The signal detection is performed by photomultipliers with directly attached readout electronics. The central component for the digitization process is a receiver chip with a low power analog to digital conversion unit and a large dynamic range. The design and prototype measurements of the included data processing unit and regulation circuits are presented. Additionally, the current status of a model of the receiver chain including future regulation possibilities are shown.

        Speaker: Ms Pavithra Muralidharan (Forschungszentrum Juelich)
      • 51
        A Low-Noise CMOS Pixel Direct Charge Sensor, Topmetal-IIa, for Low Background and Low Rate-Density Experiments

        We present the design and characterization of a CMOS pixel direct charge sensor, Topmetal-IIa, fabricated in a standard 0.35$\mu$m CMOS process. The sensor features a $45\times216$ pixel array with a 40$\mu$m pixel pitch which collects and measures external charge directly through exposed metal electrodes in the topmost metal layer. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal, which is accessible through a time-shared multiplexer. Initial tests show that the sensor achieved a $<10{e^-}$ analog noise per pixel. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gas-avalnche gain, which has unique advantages in low background and low rate-density experiments.

        Speaker: Mr Mangmang An (Central China Normal University)
      • 52
        A Micropower Readout ASIC for Pixelated Liquid Ar TPCs

        The Liquid Argon Pixel (LArPix) prototype ASIC implements 32 channels of analog front end circuitry and backend digitizers at a power consumption of less than 50 uW/channel. LArPix is envisioned as a component of a potential DUNE near detector TPC module. Demanding noise, power, and dynamic range requirements are imposed by myriad particle interaction scenarios. Widely varying track signatures with charge depositions of 1-20 MIP (15k e-/MIP) per pixel at burst rates of up to 500 kHz must be accommodated. A unique design solution for these competing requirements will be presented, including initial functionality of the June 2017 tapeout.

        Speaker: Amanda Krieger (Berkeley Lab)
      • 53
        A Monolithic HV/HR-MAPS Detector with a Small Pixel Size of 50 µm x 50 µm for the ATLAS Inner Tracker Upgrade

        This paper presents a HV/HR-MAPS detector designed in the framework of the HVCMOS collaboration for the ATLAS Inner Tracker update in the HL-LHC era. It was fabricated with a 150 nm HVCMOS process which includes a layer to isolate the bulk of PMOS transistors from the collecting node of the sensor. All front-end electronics are integrated inside the pixel, which is of only 50 µm x 50 µm, and include a preamplifier, a shaper, a discriminator and a digital block with FEI3 column drain architecture. Experimental results will be presented.

        Speaker: Raimon Casanova Mohr (Universitat Autònoma de Barcelona (ES))
      • 54
        CACTµS : High-Voltage CMOS Monolithic Active Pixel Sensor for Tracking and Time Tagging of Charged Particles

        The increase of luminosity foreseen for the Phase-II HL-LHC upgrades calls for new solutions to fight against the expected pile-up effects. One approach is to measure very accurately the time of arrival of the particles with a resolution of few tens of picoseconds. In addition, a spatial granularity better than a few millimeter will be needed to obtain a fake jet rejection rate acceptable for physics analyses. These goals could be achieved by using the intrinsic benefits of a standard High-Voltage CMOS technology -in conjunction with a high-resistivity detector material- leading to a fast, integrated, rad-hard pixel sensor ASIC.

        Speaker: Fabrice Guilloux (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
      • 55
        Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications

        This work presents the design and characterization of a SLVS transmitter/receiver pair, to be used for I/O links in High Energy Physics applications. The prototype chip was designed and fabricated in the framework of the CHIPIX65 project and was completely characterized. The chip has been also irradiated with X-rays in order to evaluate the effect of the ionizing radiation on the signal integrity. The full characterization of the driver and receiver will be discussed in the conference paper.

        Speaker: Francesco De Canio (Universita e INFN, Pavia (IT))
      • 56
        Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

        This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier.
        A thorough discussion on the design and on the characterization of the readout channel will be provided in the conference paper.

        Speaker: Davide Braga (FERMILAB)
      • 57
        Development of 4 × 28-Gbps and 4 × 14-Gbps VCSEL Array Drivers in 65 nm CMOS for HEP Applications

        We present designs and test results of two radiation-tolerant VCSEL array driver ASICs fabricated in 65 nm CMOS technology, VLAD28 and VLAD14. VLAD28 is a 4 × 28-Gbps driver, delivering 2 mA bias and 5 mA modulation currents with a power consumption of 90 mW/ch. VLAD14 is a low-power 4 × 14-Gbps driver, delivering 2 mA and 6 mA modulation with a power consumption of 44 mW/ch. The two drivers have respective innovative structures in the output stage for high-speed and low-power operation. Full-channel optical tests will be carried out in the summer and the results will be reported at the workshop.

        Speaker: Dr Di Guo (Southern Methodist University (US))
      • 58
        Development of a Front-End ASIC for 1D Detectors with 12 MHz Frame-Rate

        We present a front-end readout ASIC developed for a new family of ultra-fast 1D detectors. The ASIC is designed in 110 nm CMOS technology and is compatible with different semiconductor sensors (Si or InGaAs) and geometries. The chip contains up to 128 channels, each consisting of a Charge-sensitive Amplifier, a fully-differential shaping stage and an high-speed output buffer. A frame-rate of 12 MHz at full occupancy has been obtained with the first prototype. We also discuss a novel circuital solution to implement tunable time-variant trapezoidal shaping based on a Fully-Differential Difference Amplifier, to improve noise performance at high frame-rates.

        Speaker: Lorenzo Rota (KIT)
      • 59
        Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector

        One of the crucial parts of the proposed low occupancy Timing Vertex Detector (TVD) is a waveform sampling ASIC denoted the RFpix. It is being developed to sample and digitize voltage pulses and enable measurements of their arrival times with a timing resolution of 100fs or less. To achieve this, the RFpix needs to have an analog bandwidth of 3GHz and a sampling speed of 20GS/s. In this paper, we present the architecture of the RFpix and discuss the challenges of designing and implementing the various subcircuits necessary to achieve the required performance.

        Speaker: Mr Peter Orel (University of Hawaii at Manoa)
      • 60
        LAPA, a 5 Gb/s Modular LVDS Driver in 180 nm CMOS with Capacitively Coupled Pre-Emphasis

        A pseudo-LVDS driver has been designed in a 180 nm technology for operation up to 5 Gb/s.
        It contains parallel main driver units based on an H-bridge circuit steering a current on an external load. The number of active units is selectable,
        to reduce switching capacitance and static current, and hence power consumption, if a smaller current swing can be tolerated.
        Pre-emphasis is applied with a capacitively coupled charge-injection circuit. In nominal condition with a steering current of 4 mA over a 100 $\Omega$ termination resistor it consumes 30 mW from a 1.8 V supply.

        Speaker: Roberto Cardella (CERN)
      • 61
        MATISSE: a Low Power Front-End Electronics for MAPS Characterization

        Monolithic Active Pixel Sensors are becoming increasingly attractive for the next generation High Energy Physics experiments. For this reason several R&D are ongoing in different laboratories to improve the performance of conventional MAPS.
        In this context we present a flexible readout electronics specifically developed for the detailed characterization of MAPS. The prototype ASIC has been fabricated in 0.11 $\mu m$ CMOS technology with a die area of 2 $\times$ 2 mm$^2$ and a low voltage operation of 1.2 V.
        In the presentation, the front-end electronics will be described and detailed tests obtained on a first submission will be presented.

        Speaker: Mr Elias Jonhatan Olave (INFN di Torino e Politecnico di Torino)
      • 62
        Performance of the CATIA ASIC, the APD Readout Chip Foreseen for the CMS Barrel ECAL Electronics Upgrade at the HL-LHC

        The CMS ECAL barrel electronics will be upgraded for the HL-LHC to meet the latency and bandwidth requirements of the Phase-II Level-1 trigger system. The front-end electronics will mitigate the increasing noise from the avalanche photodiodes (APDs), discriminate against anomalous APD signals and provide improved timing information. The foreseen solution is to replace the current Charge-Sensitive-Amplifier with a Trans-Impedance Amplifier (TIA) which should provide the extra bandwidth needed to maintain the integrity of the detector signal shape. The first ASIC prototype, called CATIA, has been successfully designed in TSMC 130 nm CMOS technology and its test results will be presented.

        Speaker: Fabrice Guilloux (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
      • 63
        Prototype Chip for a Control System in a Serial Powered Pixel Detector at the ATLAS Phase II Upgrade

        A new inner tracking detector (ITk) for the Phase-II upgrade of the ATLAS experiment is in development. A serial power scheme is foreseen for the pixel detector. This requires a new detector control system (DCS) to monitor and control the pixel modules in the serial power chain.
        The Pixel Serial Power Protection (PSPP) chip is an ASIC for this purpose. It operates parallel to the modules and houses an ADC and bypass. This talk presents test results with the PSPPv3 chip. It includes irradiation up to 500Mrad and investigations of a serial power chain with up to 8A supply current.

        Speaker: Niklaus Lehmann (Bergische Universitaet Wuppertal (DE))
      • 64
        Radiation tolerant serial links for high-speed data transfer in High Energy Physics experiments

        Radiation tolerant serial links for high-speed data transmission in High Energy Physics experiments have been developed at INFN-Pisa and UCSB in a commercial 65nm CMOS technology: 2Gbps Standard-Cell based Serializer and Deserializer and custom 3GHz SLVS Driver and Receiver. Results of test and characterization of the last version of the circuit prototypes produced in the second half of 2016 and tested and characterized, including TID and SEE tests, in the first half of 2017 will be presented. The Serializer and the SLVS Drivers and Receivers have been successfully used in the CHIPIX65-FE ASIC, a demonstrator of a Front-End ASIC for pixel detectors developed at INFN.

        Speaker: Mr Guido Magazzu (INFN - Sezione di Pisa)
      • 65
        Short-Strip ASIC (SSA): A 65nm Silicon-Strip Readout ASIC for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector Upgrade at HL-LHC

        The SSA is a silicon-strip readout ASIC for the hybrid Pixel-Strip detector of the CMS Outer Tracker High Luminosity LHC (HL-LHC) Phase II upgrade. It is a 120-channel ASIC with double-threshold binary readout architecture, utilizing a quick hit cluster finding logic to provide encoded hit information for particle momentum discrimination to the Macro Pixel ASIC (MPA) at the bunch crossing rate of 40MHz, while allowing the full sensor readout at a nominal average trigger rate of 750KHz.
        The design and the implementation in a 65nm CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation will be presented in this paper.

        Speaker: Alessandro Caratelli (Microelectronic Systems Laboratory, École polytechnique fédérale de Lausanne (EPFL), Switzerland)
      • 66
        The Characterization of a Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout

        We present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel serializer ASIC for detector front-end readout. LOCx2-130 consists of two serializer channels with custom encoders and each channel operates at 4.8 Gbps. The ASIC is fabricated with a commercial 130-nm CMOS process and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a bit error rate of below 10-12 with a latency of from 34.4 ns to 40.7 ns.

        Speaker: Dr Datao Gong (Department of Physics, Southern Methodist University, Dallas, TX 75275, USA)
      • 67
        The Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

        Two optical link data transmission ASICs have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I upgrade. The latency of each ASIC and its corresponding receiver implemented in the back-end FPGA, are critically specified to be less than 150 ns. We present the latency measurements of two ASICs. The optical link latency measurement results indicate that both ASICs achieve their design goals and meet the latency specification. The consistence between the ASIC design simulation and measurements validates the ASIC characterization.

        Speaker: Dr Datao Gong (Department of Physics, Southern Methodist University, Dallas, TX 75275, USA)
      • 68
        Time-to-Digital Converter with Adjustable Resolution Using a Digital Vernier Ring Oscillator

        This paper reports the development of a high resolution, low power, and adjustable in frequency Time-to-Digital Converter (TDC), based on two vernier Ring Oscillators (RO) made of standard XOR cells. The TDC is aimed at exploiting the excellent timing performance of the multigap Resistive Plate Chambers (RPC). The frequency of each RO is adjustable thanks to a 9-bit register from 340MHz to 370MHz, allowing theoretically an LSB selection down to one picosecond. The core area measures 35 $\times$75 $\mu m^{2}$ in a 130nm CMOS technology. Under 1.2V, the TDC consumes 2.3 m$A_{RMS}$ and 260 n$A_{RMS}$ with or whithout signal respectively.

        Speaker: Ms ANNAGREBAH Amina (Universite Claude Bernard-Lyon I (FR))
      • 69
        Two High-Speed Dual-Channel VCSEL Driver

        We present two designs of a dual-channel VCSEL driver ASIC, named LOCld130 and LOCld65, aiming for the upgrade of ATLAS Liquid Argon Calorimeter. Each channel of the driver operates at 5 Gbps or 10 Gbps respectively. They are implemented in commercial 130 nm and 65 nm CMOS technologies. In typical case the 5 Gbps driver dissipates 56 mW/channel (VCSEL included) and the 10 Gbps 58 mW/channel. Both designs will be prototyped this summer.

        Speaker: Wei Zhou (Central China Normal University)
    • POSTER Session: 1 - Optoelectronics and Links Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
    • POSTER Session: 1 - Other Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 70
        DQM4HEP - A Generic Online Monitor for Particle Physics Experiments

        Currently there is a lot of activity in R&D for future colliders. Multiple detector prototypes are being tested, each with different requirements for data acquisition and monitoring, which has generated different ad-hoc software solutions. We present DQM4HEP, a generic C++11 framework for online monitoring for particle physics experiments, and results obtained at several testbeams with detector prototypes using the framework as it was developed. We also present the currently ongoing work to integrate DQM4HEP and EUDAQ, which will allow these to work together as a complete and generic DAQ and monitoring system for any detector test, as part of AIDA-2020.

        Speaker: Tom Coates (University of Sussex (GB))
      • 71
        The Calorimeter Control Card Unit

        The project of the LHCb upgrade foresees a replacement of the whole acquisition system of the detector to allow a full readout at 40 MHz. The development of a new control board, called the 3CU for the electromagnetic and hadronic calorimeters was proposed. This board receives commands from the main LHCb control system and sends them through the backplane to the front-end boards. Each calorimeter crate is equipped with one unique 3CU plugged in the central slot which also provides the clock, slow controls, and Fast Control command to all the boards inside the same crate.

        Speaker: Mr Olivier Duarte (Universite de Paris-Sud 11 (FR))
      • 72
        An FPGA-Based Sampling-ADC for the Crystal Barrel Calorimeter

        The digitization stage of the main electromagnetic calorimeter of the CBELSA/TAPS experiment in Bonn (Germany) is being equipped with custom 80 MSPS, 14 bit Sampling-ADCs. Onboard data processing with FPGAs allows determination of the signal characteristics, reducing the data substantially. The readout of the unprocessed sampling data allows offline analysis and refinement of the FPGA-algorithms.

        A partial setup has shown promising results during a photoproduction-beamtime. It has been demonstrated that the SADCs are able to overcome the readout-rate limitation of the current QDC readout.

        The full setup is planned to be commissioned within the next year.

        Speaker: Mr Johannes Müllers (Helmholtz-Institut für Strahlen- und Kernphysik)
    • POSTER Session: 1 - Packaging and Interconnects Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
    • POSTER Session: 1 - Power, Grounding and Shielding Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Porter College Dining Hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 73
        Low Voltage Powering of On-Detector Electronics for HL-LHC Experiments Upgrades

        All LHC experiments will be upgraded during the next LHC long shutdowns (LS2 and LS3). The use of more advanced CMOS technology nodes typically implies higher current consumption of the on-detector electronics. In this context, and in view of limiting the cable voltage drop, point-of-load DC-DC converters will be used on detector. This will have a direct impact on the existing powering scheme, implying new AC-DC and/or DC-DC stages as well as changes in the power cabling infrastructure. This paper will present the first results obtained while evaluating different LV powering schemes and distribution layouts for HL-LHC trackers.

        Speaker: Vincent Bobillier (CERN)
      • 74
        ATLAS ITk Short-Strip Stave Prototype Module with Integrated DCDC Powering and Control

        The prototype Barrel module design, for the Phase II upgrade of the of the new Inner Tracker (ITk) detector at the LHC, has adopted an integrated low mass assembly featuring single-sided flexible circuits, with readout ASICs, glued to the silicon strip sensor. Further integration has been achieved by the attachment of module DCDC powering, HV sensor biasing switch and autonomous monitoring and control to the sensor. This low mass, integrated module approach benefits further in a reduced width stave structure to which the modules are attached. The results of preliminary electrical tests of such an integrated module will be presented.

        Speaker: Ashley Greenall (University of Liverpool (GB))
      • 75
        Gallium Nitride DC-to-DC Converter

        High efficiency, radiation hard, hybrid GaN and CMOS integrated module DC-to-DC converter has been designed. The integrated, compact, low-mass, single-module DC-DC converter solution has an input voltage of 18V regulated down to an output voltage of 1.4V, with 5A maximum load current. It exhibits >80% efficiency. Discrete GaN transistors are used for the power stage, and the controller circuitry and power device drivers are integrated on a 0.35um CMOS chip. Radiation hardening by design (RHBD) techniques have been implemented and the goal is that the converter functions at total ionizing dose (TID) levels ≥150 megarad(Si).

        Speaker: Esko Mikkola (Alphacore, Inc.)
    • POSTER Session: 1 - Production, Testing and Reliability Porter College Dining Hall (USCS)

      Porter College Dining Hall


      Porter College Dining Hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 76
        Electrical and Functional Characterisation with Single Chips and Module Prototypes of the 1.2 Gb/s Serial Data Link of the Monolithic Active Pixel Sensor for the Upgrade of the ALICE Inner Tracking System.

        The upgrade of the ALICE Inner Tracking System uses a newly developed Monolithic Active Pixel Sensor (ALPIDE) which will populate 7 tracking layers surrounding the interaction point. Chips communicate with the readout electronics using a 1.2 Gb/s data link and a 40 Mb/s control link. Event data are transmitted to the readout electronics over microstrips on a Flexible Printed Circuit and a 5m long twinaxial cable.

        This contribution describes the experimental characterisation activity to verify the reliability of control and data transmission for single chips and prototypes of the detector modules, in laboratory setups and beam tests.

        Speaker: Matthias Bonora (University of Salzburg (AT))
      • 77
        The Quality Assurance of a Low-Latency, Low-Overhead, Dual-Channel Transmitter ASIC for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade

        We present the quality assurance (QA) test of LOCx2, a low-latency, low-overhead transmitter ASIC for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test we will screen about 7000 LOCx2 chips to ensure their basic functionality. The QA test system, including two printed circuit boards, firmware, software, are under development. All tests are automatically conducted and controlled by LabVEW software running on a computer. The test results will be reported.

        Speaker: Tiankuan Liu (Southern Methodist University (US))
      • 78
        The Quality Assurance Test of a VCSEL Driver ASIC for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade

        A VCSEL driver ASIC, LOCld, has been designed for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade. In total about 7000 chips have been produced and are in packaging process. We present the quality assurance test aiming at screening all functional chips before they are assembled into optical transmitter modules. A detailed test procedure is proposed. A dedicated test board has been designed and in fabrication. The test results will be present in the workshop and in the proceeding.

        Speaker: Tiankuan Liu (Southern Methodist University (US))
      • 79
        Quad Module Hybrid Development for the ATLAS Pixel Layer Upgrade

        A quad chip module hybrid—assembled with FE-I4 chips—has been fabricated to test performance in a serially powered module chain as would be used in the upgraded ATLAS pixel layer at the High Luminosity LHC. This poster present results of the development of a flex circuit board interface for the quad chip modules and system integration tests of modules installed on an I-beam. Experience from these hybrid assemblies will inform the design of a flex hybrid for the new large format readout chip, RD53A, which will be produced in 2017 by the RD53 collaboration.

        Speaker: Katherine Dunne (Lawrence Berkeley National Lab)
      • 80
        A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

        After having commissioned the readout electronics currently implemented in the Insertable B-Layer, Layer 1 and Layer 2 of the ATLAS Pixel Detector (B-Layer and Disk readout electronics in under commissioning), we have designed and fabricated a new readout electronic board looking at the upgrade of the LHC pixel detectors. A couple of PCI_express-based prototype boards, namely PCI-ROD featuring all the minimal I/Os and interfaces to address the future front-end electronics, have already been fabricated and tested. The GBTx and RD53A are the first chips that we are going to interface with: preliminary tests are here presented.

        Speaker: Prof. Alessandro Gabrielli (INFN and Physics and Astronomy Dep. University of Bologna)
      • 81
        Characterization of a Prototype Batch of Long Polyimide Cables Designed for Fast Data Transmission on ATLAS ITk Strip Staves

        The silicon-strip system in the ATLAS ITk detector has individual sensor modules mounted on staves to provide integrated solution for mechanical support, power, cooling, and data transmission. The data and power are transmitted to individual modules on polyimide tapes placed on thermo-mechanical stave cores. The 1.4 m long tapes transmit module data at rates up to 640 Mbps, several multi-drop clock and command links, and power lines. The first batch of 25 tapes has been produced. We characterized the line impedance and its variation across the batch, examined the tape cross-section, and assessed the variation between design and fabrication.

        Speaker: Vitaliy Fadeyev (University of California,Santa Cruz (US))
      • 82
        Electro-Migration Driven Failures on Miniature Silver Fuses at the Large Hadron Collider

        In the Large Hadron Collider (LHC), the cryogenics instrumentation infrastructure uses fuse-protected high-voltage isolated temperature transducer cards. Spurious faults were observed at their miniature silver fuses during the periods 2008-2010 and 2014-2016 and a study was launched to understand the underlying failure mechanism.

        The study uses data from Scanning Electron Microscopy (SEM), spectrometry, Weibull reliability calculations, operating temperature profiles and existing data logging tools. For the period 2014-2016, the fuse failures followed a Weibull distribution of β = 3.91 and η = 2323 days. The leading failure mechanism was attributed to electro-migration phenomena.

        Speaker: Nikolaos Trikoupis (CERN)
    • Optoelectronics and Links Earth and Marine Sciences (E&MS) Building (UCSC)

      Earth and Marine Sciences (E&MS) Building


      Convener: Ferdinand Hahn (CERN)
    • Production, Testing and Reliability Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Convener: Philippe Farthouat (CERN)
      • 84
        ATLAS ITk Short-Strip Stave Prototypes with 130nm Chipset

        The ATLAS ITk is working to deliver a new Inner Tracking detector for use at HL-LHC. The strip tracker community has recently constructed partially loaded, double sided demonstrator staves using the HCC / ABC130 chipset in 130nm CMOS technology. Mindful of the need to maximise power efficiency whilst minimising the cost and material of associated cable plant, the system design includes the integration of a low-mass DC-DC converter and sensor bias (HV) switch within each module. This paper documents the first results from the demonstrator staves. The system concept and the roadmap toward a full system test are also outlined.

        Speaker: Peter Phillips (STFC - Rutherford Appleton Lab. (GB))
      • 85
        A Compact Size, 64-Channel, 80 MSPS, 14-Bit Dynamic Range ADC Module for the PANDA Electromagnetic Calorimeter

        A compact-size, 64-channel, 80 MSPS, 14-bit dynamic range ADC module for the scintillating electromagnetic calorimeter of PANDA was developed, tested in various detector readout set-ups and are currently in mass production phase. The module performs signal filtration, extract important signal parameters and allow for resolving and parametrizing overlapping pulses. Processed data are pushed to optical links running at 2 Gbit/s. The ADC module is equipped with a PLL phase noise cleaner and allows for defined latencies. 225 of these modules will be placed inside of the PANDA detector volume, exposed to magnetic field of up to 2T and a non-negligible radiation flux.

        Speaker: Pawel Marciniewski (Uppsala University)
      • 86
        A Combined Versatile Platform for Silicon Strip Hybrids Reliability Assessment

        A unified platform combining a low noise 64-channel power supply with environmental monitoring and a high data rate transmission system, rated up to 1.2 Gbps/sec, has been developed for commissioning of the ATLAS ITk silicon strip hybrids. The power supply with 10mV peak-to-peak noise, implements 3kV isolation and software control. Humidity, temperature, voltage and current are monitored for all channels through I2C interface. Data paths are organized in a pyramid-like, fully programmable layout, enabling use of 8 LVDS lines for accessing all 64 data inputs. The system has been optimized to fit in a single 6U VME type C crate.

        Speaker: Evangelos Gkougkousis (Conseil Europeen Recherche Nucl. (CERN)-Unknown-Unknown)
    • Other Earth and Marine Sciences (E&MS) building (UCSC)

      Earth and Marine Sciences (E&MS) building


      Earth and Marine Sciences (E&MS) building
      Convener: Ferdinand Hahn (CERN)
      • 87
        Timing and Position Measurements with Ultra-Fast Silicon Detectors

        We report on the design and performance of UFSD (Ultra-Fast Silicon Detectors) and their challenge for electronics systems. UFSD are segmented thin Low-gain Avalanche Detectors (LGAD) with measured time resolution of 30ps.
        The combined accurate measurement of time and position for charged particle in UFSD offers unique physics capabilities such that they are being considered for use in the HL-LHC by ATLAS and CMS because of their ability to suppress backgrounds from high-luminosity pile-up.
        We describe the status of the R&D involving three manufacturers (CNM, FBK, HPK) and radiation campaigns up to a neutron fluences of 6e15 n/cm^2 permits and assess the special challenges their use in HL-LHC would entail.

        Speaker: Hartmut Sadrozinski (SCIPP, UC santa Cruz)
      • 88
        CERN-IPMC Solution for AdvancedTCA Blades

        The AdvancedTCA standard has been selected as one hardware platform for the upgrades of the back-end electronics of the CMS and ATLAS experiments of the Large Hadron Collider. In this context, the CERN EP-ESE group has designed and produced an IPMC mezzanine card for the management of AdvancedTCA blades. This paper presents the CERN-IPMC hardware and the software environment to be used for its customization and describes a test pad that can also be used as a development kit. Finally, it also introduces the foreseen conditions for distributing the module.

        Speaker: Julian Maxime Mendez (CERN)
    • 9:45 AM
      Coffee break
    • Invited Talk Earth and Marine Sciences (E&MS) Buillding (UCSC)

      Earth and Marine Sciences (E&MS) Buillding


      Earth and Marine Sciences (E&MS) Buillding
      Convener: Julie Whitmore (Fermi National Accelerator Lab. (US))
      • 89
        Readout Electronics Systems for Liquid Argon TPCs in Neutrino Experiments

        R&D studies of readout electronics systems for accelerator based neutrino experiments have been carried out since 2008. The CMOS based cryogenic readout electronics is the enabling technology for giant (> 10kT) LAr TPC (Liquid Argon Time Projection Chamber) in neutrino experiments, which also has potential to be used in other noble liquid TPC based experiments (dark matter search, neutrino- less double beta decay, etc.). The readout integrated with active detector is an important concept being followed in the development of readout electronics systems in LAr TPC experiments.
        The readout electronics system for neutrino experiments in Short Baseline Neutrino Program (MicroBooNE and SBND) and Long Baseline Neutrino Program (DUNE) will be presented, where CERN Neutrino Platform has significant involvement in both programs. The readout electronics system for ProtoDUNE-SP currently being installed in EHN1 at CERN will be described in detail. Performance studies of cryogenic readout electronics systems will be presented.

        Speaker: Hucheng Chen (Brookhaven National Laboratory (US))
    • ASIC Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Ping Gui (Southern Methodist University (US))
      • 90
        Laboratory and Beam Test Results of TOFFEE ASIC and Ultra Fast Silicon Detectors

        We report on the measurements performed on the full custom ASIC TOFFEE designed to read out Ultra Fast Silicon Detectors (UFSD). The ASIC has been tested in laboratory with custom test boards and an infrared laser hitting the sensor and emulating a minimum ionizing particle signal.
        Laser measurements showed that a time resolution of less than 50 ps is achievable with a 10 fC signal.
        We will also present the beam test results for the TOFFEE and UFSD system which will be held in May at CERN.

        Speaker: Roberta Arcidiacono (Universita e INFN Torino (IT))
      • 91
        Design and Characterisation of the Monolithic Matrices of the H35DEMO Chip

        The H35DEMO chip is a HV/HR-MAPS demonstrator of 18.49 mm x 24.4 mm, fabricated with a 0.35 µm HVCMOS process from AMS in four different substrate resistivities. The chip is divided into four independent matrices with a pixel size of 50 µm x 250 µm. Two of the matrices include all the digital readout electronics at the periphery. This contribution describes the two standalone matrices of the H35DEMO chip and will present the results of two testbeams carried out with unirradiated and irradiated samples with different substrate resistivities.

        Speaker: Raimon Casanova Mohr (Universitat Autònoma de Barcelona (ES))
      • 92
        KlauS4: A Multi-Channel Silicon-Photomultiplier Charge Readout ASIC in 0.18 μm UMC CMOS

        KLauS4 is a 7-channel mixed-mode Silicon-Photomultiplier readout ASIC for imaging calorimetry at a possible future linear collider, where one key aspect is the low-power consumption of the readout ASICs. Each channel consists of a low-noise front-end with two gain branches to deal with a large input signal range, and a 10-bit power efficient SAR ADC to digitize the charge information; a common digital part for data storage and transmission is also implemented into this chip. For each channel, an additional pipelined stage is used to increase the quantization resolution to 12-bit when necessary. Detailed design of the ASIC, results on characterization measurements and first test-beam results will be presented.

        Speaker: Vera Stankova
      • 93
        A high-Precision Timing ASIC for TOF-PET Applications

        Detectors with precise time-of-flight measurement capabilities are a very active area of research in particle physics and imaging, due to their improved accuracy and background rejection. In this contribution we present a monolithic readout ASIC, developed for a novel PET scanner, featuring a 30 ps time resolution for 511 keV photons using a SiGE HBT based front-end, capable of driving large input capacitances (up to 1 pF) while using less than 150 µW/channel. A fully-functional prototype has been submitted to IHP and a full version is in an advanced stage of design.

        Speaker: Pierpaolo Valerio (CERN)
    • Systems, Planning, Installation, Commissioning and Running Experience Thimann I lecture hall (UCSC)

      Thimann I lecture hall


      Thimann I lecture hall
      Convener: Ferdinand Hahn (CERN)
      • 94
        Demonstrating TTC-PON Robustness and Flexibility

        In 2016, a TTC-PON (Timing, Trigger and Control system based on Passive Optical Networks) demonstrator was presented at TWEPP as an alternative to replace the TTC system, currently responsible for delivering timing, trigger and control commands in the LHC experiments. Towards a deployment foreseen for ALICE phase-1 upgrade, the system has been consolidated through flexible software implementation providing full configuration, complete calibration and extended monitoring and diagnostic tools. A scaled-up setup was built with various FPGA platforms to stress the system in realistic conditions. The system and its features will be demonstrated together with a discussion on its robustness.

        Speaker: Eduardo Brandao De Souza Mendes (CERN)
      • 95
        Development of the Readout System for Triple-GEM Detectors for the CMS Forward Muon Upgrade

        We present the readout system being designed for triple-GEM detectors to be installed in 2019-2020 in the CMS muon endcap for HL-LHC. Beginning of 2017, 10 triple-GEMs have been installed in CMS. These detectors are read-out with the VFAT2 chip while its next version, the VFAT3, is under characterization. The rest of the readout system is very similar between the 2017 and the final version: on-detector FPGA board with GBTx and SCA, Versatile link and microTCA backend (CTP7). We will report on the first experience in CMS with VFAT2s as well as the status of the final system design.

        Speaker: Gilles De Lentdecker (Universite Libre de Bruxelles (BE))
      • 96
        Integration of the CMS Phase 1 Pixel Detector

        During the extended year-end technical stop 2016/17 the CMS Pixel Detector has been replaced. The new Phase 1 Pixel Detector is designed for a luminosity that could exceed L = 2x10^34 cm^-2 s^-1. With one additional layer in the barrel and the forward region of the new detector, combined with the higher hit rates as the LHC luminosity increases, these conditions called for an upgrade of the data acquisition system, which was realised based on the mircoTCA standard. This contribution focuses on the experiences with integration of the new detector readout and control system and reports on the operational performance of the CMS Pixel detector.

        Speaker: Andreas Kornmayer (CERN)
      • 97
        Integration of Intelligence and Redundancy Elements into the FPGA-Based DAQ of the COMPASS Experiment

        Using FPGA technology for event building tasks in high-energy physics experiments reduces costs and increases reliability of DAQ systems. In 2014, the COMPASS experiment at CERN’s SPS commissioned a novel, intelligent, FPGA-based DAQ (iFDAQ) in which event building is entirely performed by FPGA cards. The highly scalable system is designed to cope with an on-spill data rate of 1.5 GB/s and a sustained data rate of 500 MB/s. Its intelligent and highly reliable hardware event builder is able to handle and detect front-end errors and automatically take corrective action. The contribution will give an overview of system details, performance, and running experience.

        Speaker: Dominik Steffen (Technische Universitaet Muenchen (DE))
    • 1:00 PM
      Lunch Porter College Dining Hall (UCSC)

      Porter College Dining Hall


    • Invited Talk Earth and Marine Sciences (E&MS) Buillding (UCSC)

      Earth and Marine Sciences (E&MS) Buillding


      Earth and Marine Sciences (E&MS) Buillding
      Convener: Christophe De La Taille (OMEGA (FR))
      • 98
        Beyond 100Gbps High-Speed Optical Data Interconnects

        Modern data acquisition techniques employed in particle physics create large amounts of digital data that must be transmitted to remote electronics and computers for further processing. Increasingly, bandwidth requirements preclude the use of PCB traces and traditional copper cabling, even for modest interconnection length. Fortunately, novel copper and optical flyover solutions are being developed to go around the limits of traditional PCB and cabling, enabling transport of data at rates exceeding 28 Gb/s per lane over a range of distances. We will describe advances in miniature, very high speed connectors, micro-coax and micro-twinax cabling, and on board optical transceivers that can meet present and future interconnect challenges. We will show how they can be customized to the harsh environment and limited space requirements that are typical of these applications.

        Speaker: Marc Verdiell (Samtec Optical Group)
    • Working Group: FPGA Natural Sciences Annex (UCSC)

      Natural Sciences Annex


      Convener: Salvatore Danzeca (CERN)
    • Working Group: Micro-electronics User Group Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Federico Faccio (CERN)
      • 103
        MUG Agenda
        • General news from the CERN Foundry Service Team (10min)
        • Single Event Latchup in 130nm circuits (10min)
        • Stability of the TID response of 130 and 65nm technologies (5min)
        • Total Ionising Dose response of 65nm MOSFETs irradiated to ultra-high doses (40min)
        • Plans for the simulation of irradiated transistors in 65nm CMOS (5min)
        • Plans for the evaluation of the TID effects in 40 and 28nm CMOS (5min)
        Speaker: Federico Faccio (CERN)
    • Working Group: Power Thimann I lecture hall (UCSC)

      Thimann I lecture hall


      Convener: Magnus Hansen (CERN)
    • 4:05 PM
      Group Picture
    • 4:20 PM
      Coffee break
    • POSTER Session: 2 - Programmable Logic, Design Tools and Methods Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 105
        FED Firmware Interface Testing with Pixel Phase 1 Emulator

        A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics was developed to test and validate the architecture of front-end driver (FED) firmware. The emulation, implemented on the CERN GLIB uTCA platform, drives optical transmitters to the back-end electronics. The firmware emulates the complex functions of the readout chips and Token Bit Managers and allows for possible exceptions in the output data. The emulation implements fixed data patterns and realistic simulated data to drive readouts at expected data and trigger rates. Testing software was developed to control and verify correct transmission of data and exception handling in the FED.

        Speaker: Matthew Kilpatrick (Rice University (US))
      • 106
        The FEROL40, a MicroTCA Card Interfacing Custom Point-To-Point Links and Standard TCP/IP.

        In order to accommodate new back-end electronics of upgraded CMS sub-detectors, a new FEROL40 card in the microTCA standard has been developed. The main function of the FEROL40 is to acquire event data over multiple point-to-point serial optical links, provide buffering, perform protocol conversion, and transmit multiple TCP/IP streams (4x 10Gbps) to the Ethernet network of the aggregation layer of the CMS DAQ event builder. The design of the FEROL40 and experience from operation will be discussed.

        Speaker: Dominique Gigi (CERN)
      • 107
        Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip

        Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for the Phase-II upgrade of the ATLAS and CMS detectors. The performance results of the migration to a new PCIe FPGA board, the PLDA XpressK7, will be presented.

        Speaker: Nikola Lazar Whallon (University of Washington (US))
      • 108
        Studies on the Readout of the ATLAS Inner Tracker Using Commercial Networking Hardware

        In the context of the ATLAS Phase-II upgrade, new front-end electronics is developed, which reads out the detector at higher bandwidth due to finer granularity and higher occupancy.
        Because of the high bandwidth requirements, new concepts are needed for the ATLAS ITk readout system. A new scalable approach based on many rather simple nodes is proposed to support lab setups, testing sites as well as the readout of large detector parts. This study is focused on the use of COTS networking components to reduce the costs and increase the flexibility of such a system. Results from first studies are presented.

        Speaker: Carsten Dülsen (Bergische Universitaet Wuppertal (DE))
      • 109
        Design and Implementation of Custom DMA Controller for the ALICE CRU, to Optimize Data Transfer Reducing the CPU Utilization

        The CRU (Common Readout Unit) is the new readout card that will be used in ALICE during Run 3.The card will receive detector data and it will store the information in the memory of the PC through DMA. To handle the high data throughput an Altera Arria 10 FPGA has been installed on the CRU.A custom DMA controller has been developed to optimize the DMA data transfer reducing the CPU utilization. The paper describes the details of implementation and the communication between software and firmware. It also shows the results obtained during the test concerning data throughput and PCIe usage

        Speaker: Jozsef Imrek (Hungarian Academy of Sciences (HU))
      • 110
        The New Version of the LHCb SOL40_SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade

        The LHCb experiment is currently engaged in an upgrade effort that will implement a trigger-less 40 MHz readout system. The upgraded Front-End Electronics profits from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new and final version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips, discussing the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described. First tests in FPGAs are shown.

        Speaker: Joao Vitor Viana Barbosa (CERN)
    • POSTER Session: 2 - Radiation Tolerant Components and Systems Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 111
        Concentration Card Prototype SOLAR and Readout Electronics Principle for ALICE Muon Tracking Chambers Upgrade

        In the framework of the ALICE experiment upgrade at HL-LHC, the whole electronics of the existing Muon Tracking Chambers (MCH) will be refactored with a new frontend chip and the associated readout electronics. This paper presents the design of the dedicated concentration cards ‘SOLAR’ to ensure the readout of 30,000 frontend chips. Based on the CERN GBTx and FEAST DCDC chips, allowing to work in a radiation and magnetic field environment, each of the 650 SOLAR cards can broadcast configuration, trigger and synchronization signals and gather the data of up to 80 frontend chips through up to 6 meter cables.

        Speaker: Aude Marie Grabas (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
      • 112
        The End-Of-Substructure Card for the ATLAS ITk Strip Tracker

        The End-Of-Substructure Card (EoS) is the interface between the building block of the ITk Strip Tracker and the outside world. All the control and command signals, the data and the power will be passing through it. The card concept is built around using the lpGBT chip set and the VTRx optical link. The EoS will handle up to 28 640 MBit data links and 10 GBit Downlinks and Uplinks. It will be powered using a two-stage DCDC converter system. A first prototype was developed using the GBTx chipset, supporting link speeds up to 5 Gbit. We present first performance measurements of the system including the performance of the DCDC system.

        Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE))
      • 113
        A SEU-Immune Self-Tuned Pixel Chip Architecture

        Readout chips of hybrid Pixel detectors use low power amplifier and threshold discrimination to sense and digitise charge deposited in semiconductor sensor. Due to variability in CMOS transistors each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel. In this presentation a self-adjusting threshold mechanism is presented, which corrects the threshold for both spacial and time variation. The behaviour of this circuit has been simulated to evaluate its performance compared to traditional calibration results. The simulation results show that this mechanism can perform equally well, but eliminates instability over time and is immune to single event upsets.

        Speaker: Timon Heim (Lawrence Berkeley National Lab. (US))
      • 114
        Development of a Monolithic Low Power, High Speed Pixel Sensor for Particle Tracking in High Energy Physics Experiments

        We have developed a 2nd generation high resistivity CMOS process, suited for integration of complimentary pixel circuitry. High charge collection efficiency can be maintained after neutron irradiation up to 1016 neq/cm2 when applying a depletion voltage to the backside of the 50 µm thick devices. Results measured with a 15 µm MAPS detector, fabricated in this technology, will be presented.
        Based on the Orthopix architecture, we are developing a megapixel detector with digital pixel output on 20 µm pitch supporting a frame rate of 50 MHz at a power dissipation of 200 mW/cm2. Process and design will be presented.

        Speaker: Dr Stefan Lauxtermann (Sensor Creations, Inc.)
      • 115
        General-Purpose Solution for Timepix3 – Katherine Readout

        The contribution shows possibilities of the readout for Timepix3 (Ethernet Embedded Readout Interface for Timepix3 – called Katherine) for a wide range of applications. The architecture and features of the system are described in detail. The stress is laid on the usage of more readouts in a telescope configuration, where more Timepix3 sensors are operated and their time-dependent functions are synchronized. The fully radiation hardened solution for Timepix3 is also presented. Authors demonstrate and discuss the utilization of the device in ATLAS experiment.

        Speaker: Dr Petr Burian (University of West Bohemia (CZ), Czech Technical University (CZ))
      • 116
        Design and Radiation Tests on a LED Based Emergency Evacuation directional light

        A LED (Light Emitting Diode) based directional lighting has been designed to indicate the best evacuation direction for applications like the LHC tunnel. The design includes constraints for redundancy required by safety systems and for components selection by radiation effects. Prototype lighting units were irradiated in CERN’s CHARM facility and were operational up to a Total Integrated Dose (TID) of 870 Gy. This paper describes the basic design and the irradiation effects.

        Speaker: Nikolaos Trikoupis (CERN)
      • 117
        Irradiation Test Results of the ALICE SAMPA ASIC

        This paper will present the irradiation test results performed on the first two prototypes (MPW1 and V2) for the new readout ASIC (SAMPA). The SAMPA chip is aimed to be used in the ALICE Time Projection Chamber detector (TPC) and ALICE Muon Chamber (MCH) detector during RUN3 starting in 2021. The irradiation tests have been performed using proton beams of 180 MeV.

        Speaker: Sohail Musa Mahmood (University of Oslo (NO))
      • 118
        Rad-Hard Fibre Optics Cabling Design for LHC Detectors Upgrades

        Upgrades over the next decades will enable LHC to operate at a higher luminosity (HL-LHC). Accordingly, the optical links designed to transmit collision data should be hardened against increased radiation levels, allowing for a reliable communication. This paper studies fibre cabling design of a generic link between the in-detector optical front-end and the counting room. The proposed solution concatenates radiation-resistant and conventional fibres using multi-fibre interconnections. The radiation penalty calculation considers a temperature of ‒30°C inside the detector innermost part. The maximum link loss during HL-LHC lifetime is estimated to be 3.16dB, complying with predefined margins of Versatile Link system.

        Speaker: Jeremy Blanc (CERN)
    • POSTER Session: 2 - Systems, Planning, Installation, Commissioning and Running Experience Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 119
        Readout Electronics for the First Large HV-MAPS Chip for Mu3e

        Readout Electronics for the First Large HV-MAPS Chip for Mu3e

        Mu3e is an upcoming experiment searching for charged lepton flavor violation in the rare decay mu->eee. A silicon pixel tracker based on 50 um thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1T magnetic field will deliver precise vertex and momentum information. The MuPix HV-MAPS chip combines pixel sensor cells with integrated analog electronics and a complete digital readout. For the characterization of the first large MuPix system on chip a dedicated readout system was developed.

        The dedicated readout chain and the first results from the characterization of the large scale MuPix prototype will be presented.

        Speaker: Dirk Wiedner (Ruprecht-Karls-Universitaet Heidelberg (DE))
      • 120
        A Compact Tiled Readout for Hamamatsu H13700 PMTs with 256 Pixels

        Recent advances in light detectors has led to the introduction of a number of highly pixelated but compact photomultiplier tubes. These PMTs require compact readout electronics that directly couple to the PMTs, are high performance and can provide timing resolution on par with the PMT. In this paper we propose a compact readout device for the Hamamatsu H13700 PMT with 256 pixels. The design is based on the TARGETX waveform sampling chip developed at the University of Hawaii. The proposed electronics allow for tile assembly and operation for multiple of such PMTs.

        Speaker: Isar Mostafanezhad (Nalu Scientific, LLC)
      • 121
        KALYPSO: a 1D Detector for High-Repetition Rate Experiments at Light Sources

        KALYPSO is a 1D imaging detector with 10 MHz frame-rate developed for high repetition-rate experiments, such as electro-optical beam profile measurements with sub-ps resolution at ANKA and Eu-XFEL. KALYPSO consists of a Si or InGaAs microstrip sensor coupled to a front-end readout, integrated with an FPGA readout card. A Low Gain Avalanche Diode (LGAD) sensor is being developed to improve the time resolution. A DAQ framework transmits data to external GPU-based clusters, where data is processed in real-time at 7 Gbytes/s and a latency in the order of a few μs. We describe the system and the experimental results.

        Speaker: Lorenzo Rota (KIT)
      • 122
        Next Generation ATCA Control Infrastructure for the CMS Phase-2 Upgrades

        A next generation control infrastructure to be used in Advanced TCA (ATCA) blades at CMS experiment is being designed and tested. Several ATCA systems are being prepared for the High-Luminosity LHC (HL-LHC) and will be installed at CMS during technical stops. The next generation control infrastructure will provide all the necessary hardware, firmware and software required in these systems, decreasing development time. It includes an Intelligent Platform Management Controller (IPMC), a Module Management Controller (MMC) and an Embedded Linux Mezzanine (ELM) processing card. The chosen architectures, their testability, integration and the advantages over existing solutions will be discussed.

        Speaker: Wesley Smith (University of Wisconsin-Madison (US))
      • 123
        ATCA Thermal Management Study for the ATLAS Phase-II Upgrade

        The AdvancedTCA (ATCA) telecom industry standard has been selected as the hardware platform for the “Phase-II Upgrade” of ATLAS at the Large Hadron Collider (LHC) at CERN.
        In November 2014 a project dedicated to the study of the impact of the ATCA integration in the actual counting rooms was launched analyzing the impact on the cooling infrastructures. A spare rack equipped with two ATCA shelves, high power dissipating load blades, temperature and air velocity sensors were installed in a lab. Vertical and horizontal cooling performance were checked and some critical aspects identified.
        The test results will be presented.

        Speaker: Dr Claudio Bortolin (CERN)
      • 124
        ATLAS Phase-II-Upgrade Pixel Data Transmission Development

        The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

        Speaker: Jason Nielsen (University of California,Santa Cruz (US))
      • 125
        Commissioning Experience and Upgrade Plans of the Pixel Luminosity Telescope for Luminosity Measurement at CMS

        The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors. It was installed during LS1 and has been providing luminosity measurements throughout Run 2. The online bunch-by-bunch luminosity measurement employs the "fast-or" capability of the pixel readout chip (PSI46) to quickly identify likely tracks at the full 40MHz interaction rate. In addition, the full pixel information is read out at a lower rate, allowing for more detailed offline analysis. In this talk, we will present details of the commissioning and operational history of the currently installed hardware and experience with offline analysis, in addition to upgrade plans for LS2.

        Speaker: Andres Guillermo Delannoy Sotomayor (University of Tennessee (US))
      • 126
        Commissioning of ROD Boards for the Entire ATLAS Pixel Detector

        ATLAS Experiment has reworked and upgraded some systems during the 2014-2016 LHC shut down and the Pixel Detector has inserted an additional layer: the Insertable B-Layer. The layers 1 and 2 have been also upgraded, using the same BOC and ROD cards designed for IBL, while maintaining the detector unchanged. Now the efforts focus on the upgrade of the B-Layer and the Disks, again leaving the sensors untouched. Time plan is to commission the DAQ installation by the technical stop in 2018 while IBL, Layers 1 and 2 are working and able to take data using the new readout system.

        Speaker: Prof. Alessandro Gabrielli (INFN and Physics and Astronomy Dep. University of Bologna)
      • 127
        Data Acquisition Board for a Beam-Tagging Hodoscope Used in Hadrontherapy Monitoring

        This paper presents a data acquisition board associated with a beam-tagging hodoscope to be used in hadrontherapy for ion-range monitoring. The board was designed to couple to a 64-channel multi-anode photomultiplier, and to meet the hodosope’s requirements: 1-mm spatial resolution and 1-ns temporal tagging resolution, with 100-MHz counting rate capability. It mainly consists of two 32-channel readout ASICs, a signal-processing&control FPGA and a 3-Gbit/s optical transceiver to a µTCA-based data acquisition system. The board was fabricated and its operation was verified by test bench. Beam tests (with hodoscope and acquisition system) have been scheduled and are being prepared.

        Speaker: ANNAGREBAH Amina
      • 128
        Design of the New Front-End Electronics for the Readout of the Upgraded CMS Electromagnetic Calorimeter for the HL-LHC

        At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with a challenging increase in the number of interactions per bunch crossing and radiation levels. The ECAL front-end readout electronics was completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a faster pre-amplifier, increase the sampling frequency from 40 MHz to 160 MHz and implement a trigger system that resides entirely off-detector. The design of this new electronics will be presented along with the test results of the first prototypes.

        Speaker: Fabrice Guilloux (CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
      • 129
        Design Studies for the Off-Detector Electronics of the Upgraded CMS Electromagnetic Calorimeter for the HL-LHC

        At the high-luminosity upgrade of the LHC (HL-LHC), the electromagnetic calorimeter of CMS (ECAL) will have to cope with an increase in the number of interactions per bunch crossing and radiation levels. CMS implements a sophisticated two-level triggering system composed of the Level-1, instrumented by custom-designed hardware boards, and a software High-Level-Trigger. The off-detector electronics has been redesigned with increased capabilities, exploiting the full granularity of the calorimeter at Level-1. The talk focuses on the new design and its expected performance, compared to the LHC Run2 in terms of trigger rate, rejection of anomalous signals, and selection efficiency for electrons and photons.

        Speaker: Stephen Goadhouse (University of Virginia (US))
      • 130
        Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

        The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40-80 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. The design of the readout chain and the status of the R&D of the components will be presented.

        Speaker: Philipp Horn (Technische Universitaet Dresden (DE))
      • 131
        Development of Telescope Readout System Based on FELIX for Testbeam Experiments

        A testbeam telescope, based on the ATLAS IBL silicon pixel modules, has been built to investigate the possibility of using the CMOS technology in the HL-LHC upgrade of ITk. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between different front-ends and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for the testbeam telescope, including a FMC Telescope Readout Card for data transmission. The test results show that it is capable of high-density pixel sensor calibration and readout effectively, and being deployed in the testbeam experiments.

        Speaker: Weihao Wu (Brookhaven National Laboratory (US))
      • 132
        Electronics and Firmware of the Belle II Silicon Vertex Detector Readout System

        The Silicon Vertex Detector of the Belle II Experiment at the KEK in Tsukuba, Japan, consists of 172 double-sided strip sensors. They are read out by 1748 APV25 chips, and the analogue data are sent out of the radiation zone to 48 modules which convert them to digital. FPGAs then compensate line signal distortions using digital finite impulse response filters and detect data frames from the incoming stream. Then they perform pedestal subtraction, common mode correction and zero suppression, and calculate the peak timing and amplitude of each event from a set of data samples using a neural network.

        Speaker: Richard Thalmeier (Austrian Academy of Sciences (AT))
      • 133
        Readout Electronics System of the CASCA Front-End Chip for the TPC Based X-Ray Polarimeter

        The CASCA is a 32-channal readout ASIC designed for the TPC based X-ray Polarimeter (XTP). We propose a prototype Readout system of the CASCA chip for the XTP. The system mainly consists of three kinds of modules. The ASIC cards, mounted with CASCA chip, are designed for sampling XTP signals. The Adapter card, edged-mounted with the ASIC card, is in charge of digitizing the output from ASIC card. The Master card provides 8 channels for 8 Adapter cards based Serial-Rapid-IO protocol at 6.25Gbps bandwidth, and transfers data through 10 Gigabit Ethernet, therefore 256 electronics channels are achieved.

        Speaker: Mr Liu HengShuang
      • 134
        Simulation of the ATLAS New Small Wheel Trigger System

        The instantaneous luminosity of the LHC at CERN will be increased up to a factor of seven with respect to the original design value to explore higher energy scale. The first station of the ATLAS muon end-cap Small Wheel system need to replaced by a New Small Wheel (NSW) detector. The NSW provide precise track segment information to the muon Level-1 trigger to reduce fake triggers. This contribution will summarize a detail simulation of the NSW trigger decision system, track reconstruction algorithm implemented into the trigger processor and results of performance studies on the trigger system.

        Speaker: Tomoyuki Saito (University of Tokyo (JP))
      • 135
        The TrainBuilder Data Acquisition System for the European-XFEL

        The TrainBuilder is an ATCA based data acquisition system developed at the STFC Rutherford Appleton Laboratory to provide readout for each of three Mega-pixel detectors at the European-XFEL Hamburg. Each Train Builder system constructs over 5,000 detector images per second using FPGAs with DDR2 data buffering and an analogue crosspoint switch architecture; thereby processing 10 GBytes/sec of raw image data. The TrainBuilder I/O links operate with 10 Gigabit Ethernet protocols implemented in FPGA logic. The first TrainBuilder was delivered to Eu-XFEL in August 2016 and three are now being used to commission detectors for first X-Ray beams later this year.

        Speaker: Dr John Coughlan (STFC - Rutherford Appleton Lab. (GB))
      • 136
        Upgrade of the ATLAS Monitored Drift Tube Frontend Electronics for the HL-LHC

        To cope with large amount of data and high event rate expected from the planned High-Luminosity LHC (HL-LHC) upgrade, the ATLAS monitored drift tube (MDT) readout electronics will be replaced. In addition, the MDT detector will be used at the first-level trigger to improve the muon transverse momentum resolution and reduce the trigger rate. A new trigger and readout system has been proposed. Prototypes for two frontend ASICs and a data transmission board have been tested, and simulation of the latency has been performed. We will present the overall design and focus on latest results obtained for the two ASICs.

        Speaker: Xueye Hu (Umich)
    • POSTER Session: 2 - Trigger Porter College Dining Hall (UCSC)

      Porter College Dining Hall


      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 137
        A Multi-Level Triggering System for the Mini-EUSO UV Telescope

        Mini-EUSO is a telescope and detector designed by the JEM-EUSO Collaboration to observe the UV emission of the Earth from the vantage point of the International Space Station (ISS) in an Earth orbit of around 400 Km. The main goal of the mission is to map the Earth in the UV, thus increasing the technological readiness level of future EUSO experiments and to lay the basis for the detection of Extreme Energy Cosmic Rays from space.
        This article introduces the motivation behind the Mini-EUSO multi-level trigger idea, details the readout hardware chain and reports test results on the trigger logic.

        Speaker: Mr Federico Fausti (Polytechnic University of Turin, INFN Turin)
      • 138
        The NaNet Project: Heterogeneous Real-Time Stream Processing in the Low Level Trigger of the NA62 Experiment

        Our work aims at improving the performances of the NA62 low-level trigger implementing a real-time stream processing architecture based on an orchestrated combination of heterogeneous computing devices (CPUs, FPGAs and GPUs).
        To enable it we devised NaNet, a FPGA-based PCI-Express Network Interface Card with processing and GPUDirect capabilities, which supports multiple link technologies (1/10/40GbE and custom ones).
        We have demonstrated the effectiveness of the method by retrofitting the RICH detector to generate refined physics-related primitives.
        Results obtained during the first months of 2017 run are presented and discussed, along with a description of the latest developments in the NaNet architecture.

        Speaker: Alessandro Lonardo (Sapienza Universita e INFN, Roma I (IT))
      • 139
        Functionality and Performance of the ALFA_CTPIN Module

        During first long stoppage (LS1) of the LHC, the Central Trigger Processor (CTP) of the ATLAS experiment has been upgraded. In addition to enriched functionality, it resulted in increasing the CTP input-output latency by 75 ns (3 cycles@40 MHz). The ALFA triggers were no longer early enough to contribute to the global ATLAS triggering. A dedicated input board, speeding up the ALFA signal processing and providing advanced monitoring of the ALFA trigger signals, has been therefore required.
        The ALFA_CTPIN module has been designed to deliver requested functionality. In this text, we will give description of it and present achieved performance.

        Speaker: Wieslaw Iwanski (University of Innsbruck (AT))
      • 140
        BDTs in the Level 1 Muon Endcap Trigger at CMS

        The first implementation of Machine Learning inside a Level 1 trigger system at the LHC is presented. The Endcap Muon Track Finder at CMS uses Boosted Decision Trees to infer the momentum of muons based on 25 variables. All combinations of variables represented by 2^30 distinct patterns are evaluated using regression BDTs, whose output is stored in 2 GB look-up tables. These BDTs take advantage of complex correlations between variables, the inhomogeneous magnetic field, and non-linear effects to distinguish high momentum signal muons from the overwhelming low-momentum background. The new algorithm reduced the background rate by a factor of two compared to the previous analytic algorithm, with further improvements foreseen.

        Speaker: Jia Fu Low (University of Florida)
      • 141
        ALICE Trigger System for LHC Run 3

        The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC) system based on a Passive Optical Network (PON) system. The new trigger system has been designed as dead time free and able to transmit trigger data at 9.6 Gbps. A new universal trigger board has been designed, where by changing the FMC card, it can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON.

        Speaker: Marian Krivda (University of Birmingham (GB))
      • 142
        Data Analysis at Level-1 Trigger Level

        With ever-increasing luminosity at the LHC, optimum online data selection is getting more and more important. While in the case of some experiments (LHCb/ALICE) this task is being completely transferred to computer farms, the others - ATLAS/CMS - will not be able to do this in the medium-term future for technological, detector-related reasons. Therefore, these experiments pursue the complementary approach of migrating more of the offline and high-level trigger intelligence into the trigger electronics. The presentation will illustrate how the Level-1 Trigger of the CMS experiment and in particular its concluding stage, the so-called “Global Trigger”, take up this challenge.

        Speaker: Mr Johannes Wittmann (Austrian Academy of Sciences (AT))
      • 143
        Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3

        The ATLAS first-level Endcap Muon trigger in LHC Run-3 will
        identify muons by combining data from the Thin-Gap chamber detector (TGC) and a new detector, called the New-Small-Wheel (NSW). In order to handle data from both TGC and NSW, new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger data has also been implemented with TCP/IP instead of a dedicated ASIC. This presentation will focus on the electronics and its firmware of the ATLAS first-level Endcap Muon trigger processor board for LHC Run-3.

        Speaker: Atsushi Mizukami (High Energy Accelerator Research Organization (JP))
      • 144
        Hardware Trigger Processor for the ATLAS MDT System

        We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS muon spectrometer. The processor will fit candidate muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA blade architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

        Speaker: Thiago Costa De Paiva (Univ. Illinois at Urbana Champaign (US))
      • 145
        Simulations of Busy Probabilities in the ALPIDE Chip and the Upgraded ALICE ITS Detector

        For the LS2 upgrade of the ITS detector in the ALICE experiment at the LHC,
        a novel pixel detector chip, the ALPIDE chip, has been developed. In the event
        of busy ALPIDE chips in the ITS detector, the readout electronics may need
        to take appropriate action to minimize loss of data. A lightweight, statistical
        simulation model for the ALPIDE/ITS has been designed using the SystemC

        With the simulations we have been able to quantify the probability of busy
        situations under various conditions, which is crucial knowledge for the further
        design and development of the readout electronics.

        Speaker: Simon Voigt Nesbo (Western Norway University of Applied Sciences (NO))
      • 146
        The Development of the Global Feature eXtractor (gFEX) for the ATLAS Level 1 Calorimeter Trigger at the LHC

        During the ATLAS Phase-I upgrade, the global feature extractor (gFEX) will be designed to maintain the trigger acceptance against the increasing luminosity for the ATLAS Level-1 calorimeter trigger system. The prototypes v1 and v2 have been designed and tested in 2015 and 2016 respectively. With the lessons learned, a pre-production board with three UltraScale+ FPGAs and one ZYNQ UltraScale+, and 35 MiniPODs is implemented in an ATCA module. This board will receive coarse-granularity information from the entire ATLAS calorimeters on up to 300 optical fibers and each FPGA has 24 links to the L1Topo at the speed up to 12.8Gb/s.

        Speaker: Shaochun Tang (Brookhaven National Laboratory (US))
    • 7:00 PM
      Conference Dinner with Special Invited Talk "Talking Science with the Media: Getting Your Message Across" by Danielle Venton Coconut Grove (Santa Cruz)

      Coconut Grove

      Santa Cruz

    • Systems, Planning, Installation, Commissioning and Running Experience Thimann I lecture hall (UCSC)

      Thimann I lecture hall


      Thimann I lecture hall
      Convener: Mitchell Franck Newcomer (University of Pennsylvania (US))
      • 147
        Software Defined Radio Based Readout of Microwave SQUID Multiplexed MMC Arrays

        Metallic magnetic calorimeters (MMC) are new cryogenic detectors that offer a high resolution of single eV, a signal rise time of below 100 ns, a dynamic spectrum of several 10 keV and an almost optimal linearity. MMCs are of high interest for many experiments, such as dark matter detection or neutrino mass specification. Since pixel arrays of the sensor are read out at GHz-Frequency and each single pixel offers a fast rise time, a complex analog and digital readout system is required. This contribution will give an introduction to MMC technology in combination with the implemented readout electronics.

        Speaker: Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))
      • 148
        Prospects for a Precision Timing Upgrade of the CMS PbWO Crystal Electromagnetic Calorimeter for the HL-LHC

        The upgrade of the Compact Muon Solenoid (CMS) crystal electromagnetic calorimeter (ECAL), which will operate at the High Luminosity Large Hadron Collider (HL-LHC), will achieve a timing resolution of around 30 ps for high energy photons and electrons. We will discuss the benefits of precision timing for the ECAL event reconstruction at HL-LHC. Simulation studies on the timing properties of PbWO crystals, as well as the impact of the photosensors and the readout electronics on the timing performance, will be presented. Test beam studies, including new results from 2017, on the timing performance of PbWO crystals with various photosensors and readout electronics will be shown.

        Speaker: Colin Jessop (Notre Dame)
      • 149
        The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

        Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, and performances on prototypes will presented with the overall system design.

        Speaker: Ines Ochoa (Columbia University (US))
    • Radiation Tolerant Components and Systems Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) building
      Convener: Geoff Hall (Imperial College (GB))
      • 150
        Measurements and Simulations of Single-Event Upsets in a 28 nm FPGA

        Single-Event Upsets (SEUs) in the configuration memory of a 28 nm FPGA, used in the PANDA electromagnetic calorimeter, have been studied. Results from neutron and proton irradiations are presented. A GEANT4-based Monte Carlo simulation of SEU mechanisms in nanometric silicon volumes has been developed for studies of the energy dependence. At PANDA, a neutron flux of $1\cdot10^2$ cm$^{−2}$ s$^{−1}$ at the location of the front-end modules is expected at the lowest antiproton beam momentum and a luminosity of $1\cdot10^{31}$ cm$^{−2}$ s$^{−1}$, leading to a predicted Mean Time Between Failures of 47(10) hours per FPGA in the calorimeter.

        Speaker: Markus Preston (Stockholm University (SE))
      • 151
        Radiation Hard GaNFET High Voltage Multiplexing (HV-Mux) for the ATLAS Upgrade Silicon Strip Tracker

        The outer radii of the inner tracker (ITk) for the Phase-II Upgrade of the ATLAS experiment will consist of groups of silicon strip sensors mounted on common support structures. Lack of space creates a need to remotely disable a failing sensor from the common HV bus. We have developed circuitry consisting of a GaNFET transistor and a HV Multiplier circuit to disable a failed sensor. We will present two variants of the HV Mux circuitry and show irradiation results on individual components with an emphasis on the GaNFET results. We will also discuss the reliability of the HV Mux circuitry and show plans to ensure reliability during production.

        Speaker: David Lynn (Brookhaven National Laboratory (US))
    • 9:45 AM
      Coffee break
    • Invited Talk Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Angelo Rivetti (Universita e INFN Torino (IT))
      • 152
        CMOS Biochips: The Good, the Bad, and the Hype

        In the past two decades, there has been numerous attempts to take advantage of semiconductor solutions, broadly defined, to create high-performance biosensors and bio-molecular detection devices. The goal has always been to create molecular diagnostics technologies that offer the cost efficiency, miniaturization capabilities, and manufacturing robustness of consumer electronics devices. The outcome so far, has not been very exhilarating and unfortunately there has been few impactful products based on such efforts.

        In this talk, we will discuss the use of CMOS processes and IC’s for biotechnology in the form of integrated biochips. The focus will be not only the design, manufacturing, and the packaging tradeoffs of biochips, but also on the applications requirements and ideal use models in molecular biology. We will also discuss, in detail, the recently implemented CMOS biochips for nucleic acid (DNA/RNA) testing applications.

        Speaker: Arjang Hassibi (InSilixa)
    • ASIC Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Christophe De La Taille (OMEGA (FR))
      • 153
        Design and Characterization of the Readout ASIC for the BESIII CGEM Detector

        TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal time-of-arrival and charge measurement is provided by low-power TDCs, based on analog interpolation techniques, and Wilkinson ADCs, with a fully-digital output. The design and test results of TIGER first prototype are presented showing its full functionality.

        Speaker: Fabio Cossio (Politecnico di Torino e INFN Torino (IT))
      • 154
        Development of Depleted Monolithic Pixel Sensors in 150 nm CMOS technology for the ATLAS Inner Tracker Upgrade

        This work presents a Depleted Monolithic Active Pixel Sensor (DMAPS) prototype manufactured in LFoundry 150 nm CMOS process. The described device, named LF-Monopix01, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of ATLAS Inner Tracker upgrade for High Luminosity LHC. Implementing such device in the detector will result in a lower production cost and lower material budget compared to presently used hybrid designs. In the presentation the chip architecture will be described, followed by simulation and measurement results.

        Speaker: Piotr Rymaszewski (University of Bonn (DE))
      • 155
        FE65-P2: a Pixel Prototype Readout Chip in 65nm Technology for HL-LHC Upgrades

        We present the latest results of the FE65-P2 pixel readout test chip. This is a 64 by 64 pixel matrix on 50 um by 50 um pitch, produced in 65nm CMOS technology at the end of 2015. FE65-P2 was designed to demonstrate small pixel performance and stable operation down to 500 electron threshold even with the front end pixel amplifiers embedded in a synthesized logic environment. The FE65-P2 results inform the ongoing design of a large format (400 by 192 pixels) demonstrator readout chip to be produced by the RD53 collaboration in mid 2017.

        Speaker: Timon Heim (Lawrence Berkeley National Lab. (US))
      • 156
        Monolithic Pixel Development in 180 nm CMOS for the Outer Pixel Layers in the ATLAS Experiment

        The ATLAS experiment at CERN plans to upgrade its Inner Tracking system for the High-Luminosity LHC in 2026. After the ALPIDE monolithic sensor for the ALICE ITS was successfully implemented a 180nm CMOS Imaging Sensor technology, the process was modified to combine full sensor depletion with a low sensor capacitance (~2.5fF), for increased radiation tolerance and low analog power consumption. Efficiency and charge collection time were measured with comparisons before and after irradiation. An overview of the measurements and the ATLAS-specific development towards full-reticle size CMOS sensors and modules in this modified technology will be given

        Speaker: Thanushan Kugathasan (CERN)
    • Programmable Logic, Design Tools and Methods Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Convener: Angelo Rivetti (Universita e INFN Torino (IT))
      • 157
        FPGA Based Wireless Time Interval Measurement System with Picosecond Resolution

        We present a theoretical analysis, simulation and implementation results of an FPGA-based wireless Time Interval Measurement (TIM) system. The TIM features a single channel TDC with a Serial Peripheral Interface (SPI) and wireless transmission. The TDC is based on the Vernier ring oscillator method to achieve both high resolution and wide dynamic range. The TDC architecture with an SPI is implemented in Altera Cyclone IV Device, and a wireless ZigBee module (IEEE 802.15.4 standards) is used for transmission of the measured time interval values. The paper concludes with the description of the prototype application to investigate SPAD after-pulsing.

        Speaker: Mr Balaji Srinivasan (LICET)
      • 158
        New Slow Control FPGA IP for GBT Based Systems and Status Update of the GBT-FPGA Project

        The GBT-FPGA, part of the GBT project framework, is a VHDL-based IP designed to offer a back-end counterpart to the GBTX ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the HEP experiments. In this context, a new module named GBT-SC has been designed and released to handle the slow control fields hosted in the GBT frame for Internal Control (GBTx) and External Control (SCA). This paper presents the architecture and performance of this new module as well as an outline of recent GBT-FPGA releases and future plans.

        Speaker: Julian Maxime Mendez (CERN)
      • 159
        Characterization and Verification Environment for the 65 nm Pixel Readout-Chip RD53A

        For the Phase II Upgrade of LHC, new hybrid silicon pixel detectors are required for charged particle tracking. The RD53 collaboration is currently designing a large-scale prototype sensor readout chip “RD53A”, which will be available soon. The SiLab group at the University of Bonn is highly involved in testing/verification and several chip design tasks.

        A modular and versatile test- and data acquisition system for this next generation pixel readout is being developed to perform single-chip and module measurements. The concept and implementation of this FPGA-based system, the software framework and first test results of RD53A will be presented.

        Speaker: Marco Vogt (Universitaet Bonn (DE))
    • 1:00 PM
      Lunch Porter College Dining Hall (UCSC)

      Porter College Dining Hall


    • Invited Talk Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) Building

      Earth and Marine Sciences (E&MS) Building
      Convener: Geoff Hall (Imperial College (GB))
      • 160
        ADCs Approaching 100 GS/s

        High-performance analog-to-digital converters (ADCs) are becoming essential
        building blocks in many applications including optical communications, high-speed test
        equipment such as real-time oscilloscopes, and high-energy particle physics, etc. While several ADC architectures have been proposed, SAR (Successive Approximation Register) has become the de facto preferred design, because of its low power, small silicon area, and scalability with advanced CMOS technologies. Time-interleaving architecture is a promising way to further improve the conversion rate in a given technology and push it to 100GS/s. This talk will give an overview of high-speed time-interleaved SAR ADC design, the working principle, design challenges and possible solutions. In the end, a 64 GS/s 8-bit time-interleaved ADC implemented in a 28 nm CMOS process will be presented as an example, including the proposed design techniques, calibration methods, and silicon measurement results.

        Speaker: Ping Gui (Southern Methodist University (US))
    • Packaging and Interconnects Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Magnus Hansen (CERN)
      • 161
        Manufacturing Experience and Test Results of the PS Prototype Flexible Hybrid Circuit for the CMS Tracker Upgrade

        The CMS Tracker Phase Two Upgrade for HL-LHC requires High Density Interconnect (HDI) flexible hybrid circuits to build modules with low mass and high granularity. The hybrids are carbon fibre reinforced flexible circuits with flip-chips and passives. Three different manufacturers produced prototype hybrids for the Pixel-Strip type modules. The first part of the presentation will focus on the design challenges of this state of the art circuit. Afterwards, the difficulties and experience related to the circuit manufacturing and assembly are presented. The description of quality inspection methods with comprehensive test results will lead to the conclusion.

        Speaker: Mark Istvan Kovacs (CERN)
    • Trigger Thimann I Lecture Hall (UCSC)

      Thimann I Lecture Hall


      Convener: Julie Whitmore (Fermi National Accelerator Lab. (US))
      • 162
        Design and Performance of the Upgrade of the CMS L1 Trigger

        The upgraded CMS Level-1 trigger is designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). During the technical stop at the beginning of 2016, all the electronic boards of the CMS Level-1 trigger have been replaced and the upgraded electronics tested, and commissioned with data. The upgrade of both the Stage-1 and Stage-2 happened during the shutdown of the LS1. Smarter, more sophisticated, and innovative algorithms are now the core of the first decision layer of CMS. The upgrade reduces the trigger rate and improves the trigger efficiency for a wide variety of physics signals. In this presentation the upgraded CMS Level-1 trigger design and its performance are described.

        Speaker: Costas Fountas (University of Ioannina (GR))
      • 163
        A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs

        A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and on the Pattern Recognition Mezzanine (PRM) board has been developed as a flexible platform to test and characterize low-latency algorithms for track reconstruction and L1 Trigger generation in future High Energy Physics experiments. The demonstrator has been extensively used to test and characterize the Track-Trigger algorithms and architecture based on the use of the Associative Memory ASICs and of the PRM cards. The flexibility of the demonstrator makes it suitable to explore other solutions fully based on high-performance FPGA devices.

        Speaker: Guido Magazzu (INFN - Sezione di Pisa)
      • 164
        The ATLAS Fast Tracker System

        The Fast Tracker (FTK) system, one of the ATLAS trigger upgrades, is presently being commissioned. The information from the 100 million channels of the tracking detectors is presently exploited at the HLT only for a subset of the events or for limited detector regions due to timing limitations. The FTK system is designed to deliver full event track reconstruction for all tracks with pT above 1 GeV at a Level-1 rate of 100 kHz. This provides full track information with excellent quality at the HLT input. This high performance is obtained by using a combination of dedicated ASIC hardware based on associative memories and high performance Field Programmable Gate Arrays.

        Speaker: Tomoya Iizawa (Waseda University (JP))
    • Power, Grounding and Shielding Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Magnus Hansen (CERN)
      • 165
        Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing

        Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. For this scheme, two 2.0A Shunt-LDO (SLDO) regulators are integrated in the RD53 prototype chip (65 nm) and are used to provide constant supply voltages to its power domains from a constant input current. System level simulation studies will be presented, in which a detailed regulator design in serially powered topology is used to evaluate and optimize system parameters for different operational scenarios of HL-LHC pixel detectors. Performance results from testing prototype SLDO chips will be shown, including x-ray irradiation.

        Speaker: Stella Orfanelli (CERN)
      • 166
        A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems

        A prototype second-stage buck DC-DC converter has been designed in 130nm CMOS and fully characterized. This circuit provides up to 3A at an adjustable output voltage of 0.6-1.5V from an intermediate bus voltage of 2.5V. Hardness by design techniques have been systematically used, and the prototype successfully passed TID irradiation up to more than 200Mrad and Single Event Effects tests with a heavy ion beam. Safe integration on-board requires an optimized PCB design and bump-bonding assembly to reduce parasitic inductances along the input current path. An alternative quasi-resonant topology enabling significant reduction of the inductor size is also described.

        Speaker: Giacomo Ripamonti (Ecole Polytechnique Federale de Lausanne (CH))
    • 4:05 PM
      Coffee break
    • Working Group Summaries Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


    • Closeout Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


    • TUTORIAL: ASIC Design below 65 nm: Benefits and Challenges with Designing in Advanced CMOS Nodes Earth & Marine Sciences (E&MS) Building (UCSC)

      Earth & Marine Sciences (E&MS) Building


      Convener: Alessandro Marchioro (CERN)
      • 167
        Advance Node Impact on Physical Design and Resulting Tool Support - Electrically Aware Design Flow
        • New devices (FinFETs) and fluid guardrings
        • Double/ Multiple Patterning aka coloring
        • Gridded/ track based placement and routing methodology
        • In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks


        Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design complexity, not just for designers but also for EDA tools. The drive to reduce feature size beyond optical resolution of visible and ultra-violet light has led to multiple masks/ patterns for same layer to allow for a more compact layout. Need for greater scaling and manufacturing accuracy has led to a self-aligned fabrication process requiring gridded, unidirectional interconnects. At the same time, new devices such as tri-gate finFETS have been introduced to address power, leakage and variability associated with these processes. In addition to more restrictive and complex design rules for manufacturability and process characteristics, EDA tools need to account for changes in design methodology such as highly gridded placement and routing. This presentation will cover these tool enhancements and changes to meet the process technology requirements of these nodes, for both devices and interconnects, with focus on physical implementation.

        Speaker: Sravasti Nair (Cadence Design Systems)
      • 168
        Designing CMOS Chips Beyond 65 nm

        Moore's Law has entered a new frontier as device scaling continues to excel in 10nm and beyond. As the physical dimension of devices and interconnect are being shrunk, the design rules and the design flow, for both design community and EDA community, face unprecedented complexity. Conventional design optimization techniques also need to take the novel process technologies, such as multi-gate devices (e.g., FinFET), spacer technology, and self-aligned multiple patterning lithography, into account to achieve the best possible performance, power, and area for a design with more and more functionalities integrated into one single chip.

        In this presentation, first, we will talk about simulation technologies to handle special effects introduced by advanced process nodes, such as high transistor speed, high transistors/RC capacities and reliability effects etc. with reasonable speed and performance while maintaining spice simulation accuracy. Secondly, we will also discuss about advanced integrated simulation environment targeting for different design phases to meet the tight design window. Finally, we will touch upon the importance of system integration for advance process nodes and bring up the solution for the system integration, which include IC/Package/PCB, from both implementation and analysis point of views.

        Advanced Process Nodes Simulation Strategy
        a. Simulation challenge for advanced process nodes.
        b. Simulation technology overview
        c. Reliability simulation
        i. Aging simulation
        ii. Self-heating simulation
        iii. EMIR Simulation
        d. Summary

        Advanced integrated Simulation environment
        a. Why we need integrated simulation environment?
        b. Environment for individual block
        c. Environment for block integration.
        d. Environment for verification and regression.
        e. Summary

        . System integration: integrated IC/package/PCB together
        a. Implementation flow
        b. Analysis flow

        Speaker: Ping Chen (Cadence Design Systems)