Name: TWEPP 2017 Topical Workshop on Electronics for Particle Physics
Start: 2017-09-11T00:00:00-07:00
End: 2017-09-15T19:00:00-07:00
Location: No location set

A 2 Gsps Waveform Digitizer ASIC in CMOS 180 nm Technology (in session "ASIC")

A 2.5V Step-Down DC-DC Converter for Two-Stages Power Distribution Systems (in session "Power, Grounding and Shielding")

A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links (in session "ASIC")

A 3.2 Gbps Serial Link Transmitter for CMOS Pixel Sensors in 0.18 µm CMOS Technology (in session "POSTER Session")

A 4-Channel Parallel 56 Gb/s CMOS Optical Receiver for VCSEL-Based Optical Links (in session "POSTER Session")

A 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector Upgrade at HL-LHC (in session "POSTER Session")

A Combined Versatile Platform for Silicon Strip Hybrids Reliability Assessment (in session "Production, Testing and Reliability")

A Compact Size, 64-Channel, 80 MSPS, 14-Bit Dynamic Range ADC Module for the PANDA Electromagnetic Calorimeter (in session "Production, Testing and Reliability")

A Compact Tiled Readout for Hamamatsu H13700 PMTs with 256 Pixels (in session "POSTER Session")

A Data Acquisition System for the CLIC Vertex Detector Readout Chip. (in session "Systems, Planning, Installation, Commissioning and Running Experience")

A Digital Processing Unit of a Highly Integrated Receiver Chip for PMTs in JUNO (in session "POSTER Session")

A Full Custom ASIC for Large Area 4-Dimensional Tracking (in session "POSTER Session")

A High Luminosity LHC Track Trigger for the CMS Detector (in session "Trigger")

A high-Precision Timing ASIC for TOF-PET Applications (in session "ASIC")

A Low-Noise CMOS Pixel Direct Charge Sensor, Topmetal-IIa, for Low Background and Low Rate-Density Experiments (in session "POSTER Session")

A Micropower Readout ASIC for Pixelated Liquid Ar TPCs (in session "POSTER Session")

A Monolithic HV/HR-MAPS Detector with a Small Pixel Size of 50 µm x 50 µm for the ATLAS Inner Tracker Upgrade (in session "POSTER Session")

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC (in session "POSTER Session")

A Multi-Level Triggering System for the Mini-EUSO UV Telescope (in session "POSTER Session")

A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs (in session "Trigger")

A SEU Tolerant Latches Study for the RD53A Chip (in session "Radiation Tolerant Components and Systems")

A SEU-Immune Self-Tuned Pixel Chip Architecture (in session "POSTER Session")

ADCs Approaching 100 GS/s (in session "Invited Talk")

Advance Node Impact on Physical Design and Resulting Tool Support - Electrically Aware Design Flow (in session "TUTORIAL")

Advances in Image Sensors Technologies (in session "Invited Talk")

ALICE SAMPA-ASIC Second-Prototype Qualification Studies for LHC Run 3 and Beyond (in session "POSTER Session")

ALICE Trigger System for LHC Run 3 (in session "POSTER Session")

ALTIROC0, a 20 Pico-Second Time Resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD) (in session "ASIC")

An 8-Channel ASD in 130 nm CMOS with Superior Performance of Rise Time, Noise and Threshold Uniformity for ATLAS Drift Tube Readout at the HL-LHC (in session "ASIC")

An FPGA-Based Sampling-ADC for the Crystal Barrel Calorimeter (in session "POSTER Session")

An FPGA-Based Track Finder for the L1 Trigger of the CMS Experiment at HL-LHC (in session "Trigger")

ASICs and Readout System for a High Resolution UV Single Photon Imagining Detector (in session "POSTER Session")

ATCA Thermal Management Study for the ATLAS Phase-II Upgrade (in session "POSTER Session")

ATLAS ITk Short-Strip Stave Prototype Module with Integrated DCDC Powering and Control (in session "POSTER Session")

ATLAS ITk Short-Strip Stave Prototypes with 130nm Chipset (in session "Production, Testing and Reliability")

ATLAS Phase-II-Upgrade Pixel Data Transmission Development (in session "POSTER Session")

BDTs in the Level 1 Muon Endcap Trigger at CMS (in session "POSTER Session")

Beyond 100Gbps High-Speed Optical Data Interconnects (in session "Invited Talk")

CACTµS : High-Voltage CMOS Monolithic Active Pixel Sensor for Tracking and Time Tagging of Charged Particles (in session "POSTER Session")

CBC3: a CMS Micro-Strip Readout ASIC with Logic for Track-Trigger Modules at HL-LHC (in session "ASIC")

CERN-IPMC Solution for AdvancedTCA Blades (in session "Other")

Characterization and Verification Environment for the 65 nm Pixel Readout-Chip RD53A (in session "Programmable Logic, Design Tools and Methods")

Characterization of a 9-Decade Femtoampere ASIC Front-End for Radiation Monitoring (in session "ASIC")

Characterization of a Prototype Batch of Long Polyimide Cables Designed for Fast Data Transmission on ATLAS ITk Strip Staves (in session "POSTER Session")

Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications (in session "POSTER Session")

Clock and Trigger Distribution for ALICE Using the CRU FPGA Card (in session "Programmable Logic, Design Tools and Methods")

CMOS Biochips: The Good, the Bad, and the Hype (in session "Invited Talk")

CMS DAQ Current and Future Hardware Upgrades up to Post Long Shutdown 3 (LS3) Times (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Commissioning and First Running Experiences with the TOP Barrel PID Detector in the Belle II Experiment (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Commissioning Experience and Upgrade Plans of the Pixel Luminosity Telescope for Luminosity Measurement at CMS (in session "POSTER Session")

Commissioning of ROD Boards for the Entire ATLAS Pixel Detector (in session "POSTER Session")

Concentration Card Prototype SOLAR and Readout Electronics Principle for ALICE Muon Tracking Chambers Upgrade (in session "POSTER Session")

Data Acquisition Board for a Beam-Tagging Hodoscope Used in Hadrontherapy Monitoring (in session "POSTER Session")

Data Analysis at Level-1 Trigger Level (in session "POSTER Session")

Demonstrating TTC-PON Robustness and Flexibility (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Design and Characterisation of the Monolithic Matrices of the H35DEMO Chip (in session "ASIC")

Design and Characterization of the Readout ASIC for the BESIII CGEM Detector (in session "ASIC")

Design and Implementation of Custom DMA Controller for the ALICE CRU, to Optimize Data Transfer Reducing the CPU Utilization (in session "POSTER Session")

Design and Performance of the Upgrade of the CMS L1 Trigger (in session "Trigger")

Design and Radiation Tests on a LED Based Emergency Evacuation directional light (in session "POSTER Session")

Design and Results from a Front-End Board for Micromegas Chambers in the ATLAS New Small Wheel (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors (in session "POSTER Session")

Design of the New Front-End Electronics for the Readout of the Upgraded CMS Electromagnetic Calorimeter for the HL-LHC (in session "POSTER Session")

Design Studies for the Off-Detector Electronics of the Upgraded CMS Electromagnetic Calorimeter for the HL-LHC (in session "POSTER Session")

Designing CMOS Chips Beyond 65 nm (in session "TUTORIAL")

Development of 4 × 28-Gbps and 4 × 14-Gbps VCSEL Array Drivers in 65 nm CMOS for HEP Applications (in session "POSTER Session")

Development of a Front-End ASIC for 1D Detectors with 12 MHz Frame-Rate (in session "POSTER Session")

Development of a High-Throughput Tracking Processor on FPGA Boards (in session "Trigger")

Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Pixel Upgrades (in session "ASIC")

Development of a Monolithic Low Power, High Speed Pixel Sensor for Particle Tracking in High Energy Physics Experiments (in session "POSTER Session")

Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector (in session "POSTER Session")

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC (in session "POSTER Session")

Development of Depleted Monolithic Pixel Sensors in 150 nm CMOS technology for the ATLAS Inner Tracker Upgrade (in session "ASIC")

Development of Telescope Readout System Based on FELIX for Testbeam Experiments (in session "POSTER Session")

Development of the jet Feature EXtractor (jFEX) for the ATLAS Level 1 Calorimeter Trigger upgrade at the LHC (in session "Trigger")

Development of the New Trigger Processor Board for the ATLAS Level-1 Endcap Muon Trigger for Run-3 (in session "POSTER Session")

Development of the Readout System for Triple-GEM Detectors for the CMS Forward Muon Upgrade (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade (in session "Systems, Planning, Installation, Commissioning and Running Experience")

DQM4HEP - A Generic Online Monitor for Particle Physics Experiments (in session "POSTER Session")

DRM2: the Readout Board for the ALICE TOF Upgrade (in session "Programmable Logic, Design Tools and Methods")

Effect of Gamma Irradiation on Leakage Current in CMOS Readout Chips for the ATLAS Upgrade Silicon Strip Tracker at the HL-LHC (in session "Radiation Tolerant Components and Systems")

Electrical and Functional Characterisation with Single Chips and Module Prototypes of the 1.2 Gb/s Serial Data Link of the Monolithic Active Pixel Sensor for the Upgrade of the ALICE Inner Tracking System. (in session "POSTER Session")

Electro-Migration Driven Failures on Miniature Silver Fuses at the Large Hadron Collider (in session "POSTER Session")

Electronics and Firmware of the Belle II Silicon Vertex Detector Readout System (in session "POSTER Session")

FE65-P2: a Pixel Prototype Readout Chip in 65nm Technology for HL-LHC Upgrades (in session "ASIC")

FED Firmware Interface Testing with Pixel Phase 1 Emulator (in session "POSTER Session")

FELIX: the New Detector Readout System for the ATLAS Experiment (in session "Trigger")

First results on KINTEX-7 FPGA testing in mixed field radiation at CHARM facility (in session "Working Group")

FPGA Based Wireless Time Interval Measurement System with Picosecond Resolution (in session "Programmable Logic, Design Tools and Methods")

Functional Tests of 2S Modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-Based Readout System (in session "Production, Testing and Reliability")

Functionality and Performance of the ALFA_CTPIN Module (in session "POSTER Session")

Gallium Nitride DC-to-DC Converter (in session "POSTER Session")

General-Purpose Solution for Timepix3 – Katherine Readout (in session "POSTER Session")

Hardware Trigger Processor for the ATLAS MDT System (in session "POSTER Session")

High speed links in AMC40/PCIe40 (in session "Working Group")

Integration of Intelligence and Redundancy Elements into the FPGA-Based DAQ of the COMPASS Experiment (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Integration of the CMS Phase 1 Pixel Detector (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Irradiation Test Results of the ALICE SAMPA ASIC (in session "POSTER Session")

KALYPSO: a 1D Detector for High-Repetition Rate Experiments at Light Sources (in session "POSTER Session")

KlauS4: A Multi-Channel Silicon-Photomultiplier Charge Readout ASIC in 0.18 μm UMC CMOS (in session "ASIC")

Laboratory and Beam Test Results of TOFFEE ASIC and Ultra Fast Silicon Detectors (in session "ASIC")

LAPA, a 5 Gb/s Modular LVDS Driver in 180 nm CMOS with Capacitively Coupled Pre-Emphasis (in session "POSTER Session")

LCLS-II: A High Repetition Rate X-Ray Laser Facility (in session "Invited Talk")

Low Jitter, Radiation Hardened by Design, 2.56 Gbps LVDS/SLVS Based Receiver for Analog Time Transmission (in session "POSTER Session")

Low Voltage Powering of On-Detector Electronics for HL-LHC Experiments Upgrades (in session "POSTER Session")

Manufacturing Experience and Test Results of the PS Prototype Flexible Hybrid Circuit for the CMS Tracker Upgrade (in session "Packaging and Interconnects")

MATISSE: a Low Power Front-End Electronics for MAPS Characterization (in session "POSTER Session")

Measurements and Simulations of Single-Event Upsets in a 28 nm FPGA (in session "Radiation Tolerant Components and Systems")

Methodology, experimental testing and results for the evaluation of Kintex-7 operation in radiation environment (in session "Working Group")

Monolithic Pixel Development in 180 nm CMOS for the Outer Pixel Layers in the ATLAS Experiment (in session "ASIC")

MUG Agenda (in session "Working Group")

Multi-Gigabit Wireless Data Transfer for High Energy Physics Applications (in session "POSTER Session")

MuTRiG: A Silicon Photomultiplier Readout ASIC with High Timing Precision and High Event Rate Capability (in session "ASIC")

NEBULA Large Band Digitiser for Radio Astronomy (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Neuron detectors: electrical and optical interactions with neural networks. (in session "Invited Talk")

New Slow Control FPGA IP for GBT Based Systems and Status Update of the GBT-FPGA Project (in session "Programmable Logic, Design Tools and Methods")

Next Generation ATCA Control Infrastructure for the CMS Phase-2 Upgrades (in session "POSTER Session")

Opening (in session "Opening and Welcome")

Performance of the CATIA ASIC, the APD Readout Chip Foreseen for the CMS Barrel ECAL Electronics Upgrade at the HL-LHC (in session "POSTER Session")

Power Working Group (in session "Working Group")

Prospects for a Precision Timing Upgrade of the CMS PbWO Crystal Electromagnetic Calorimeter for the HL-LHC (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Prototype Chip for a Control System in a Serial Powered Pixel Detector at the ATLAS Phase II Upgrade (in session "POSTER Session")

Quad Module Hybrid Development for the ATLAS Pixel Layer Upgrade (in session "POSTER Session")

Quality Control Considerations for the Development of the Front End Hybrid Circuits for the CMS Outer Tracker Upgrade (in session "Production, Testing and Reliability")

Rad-Hard Fibre Optics Cabling Design for LHC Detectors Upgrades (in session "POSTER Session")

Radiation Hard GaNFET High Voltage Multiplexing (HV-Mux) for the ATLAS Upgrade Silicon Strip Tracker (in session "Radiation Tolerant Components and Systems")

Radiation Hardness Studies and Evaluation on SRAM-Based FPGA for High Energy Physics Experiments (in session "Radiation Tolerant Components and Systems")

Radiation tolerant serial links for high-speed data transfer in High Energy Physics experiments (in session "POSTER Session")

Readout Electronics for the First Large HV-MAPS Chip for Mu3e (in session "POSTER Session")

Readout Electronics System of the CASCA Front-End Chip for the TPC Based X-Ray Polarimeter (in session "POSTER Session")

Readout Electronics Systems for Liquid Argon TPCs in Neutrino Experiments (in session "Invited Talk")

Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC (in session "ASIC")

SEE Tolerant Standard Cell Based Design While Guaranteeing Specific Distance Between Memory Elements (in session "Programmable Logic, Design Tools and Methods")

Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing (in session "Power, Grounding and Shielding")

Short-Strip ASIC (SSA): A 65nm Silicon-Strip Readout ASIC for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector Upgrade at HL-LHC (in session "POSTER Session")

Simulation of the ATLAS New Small Wheel Trigger System (in session "POSTER Session")

Simulations of Busy Probabilities in the ALPIDE Chip and the Upgraded ALICE ITS Detector (in session "POSTER Session")

SmartFusion2 and Arty7 radiation test results for the new developments (in session "Working Group")

Software Defined Radio Based Readout of Microwave SQUID Multiplexed MMC Arrays (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Studies on the Readout of the ATLAS Inner Tracker Using Commercial Networking Hardware (in session "POSTER Session")

Test Vehicles for CMS HGCAL Readout ASIC (in session "ASIC")

The ATLAS Fast Tracker System (in session "Trigger")

The ATLAS Muon-to-Central Trigger Processor Interface for the Phase-I Muon Trigger Upgrade (in session "Trigger")

The Calorimeter Control Card Unit (in session "POSTER Session")

The Characterization of a Low-Power, Low-Latency, Dual-Channel Serializer ASIC for Detector Front-End Readout (in session "POSTER Session")

The Development of Front-End Readout Electronics for ProtoDUNE-SP LAr TPC (in session "Production, Testing and Reliability")

The Development of the Global Feature eXtractor (gFEX) for the ATLAS Level 1 Calorimeter Trigger at the LHC (in session "POSTER Session")

The End-Of-Substructure Card for the ATLAS ITk Strip Tracker (in session "POSTER Session")

The FEROL40, a MicroTCA Card Interfacing Custom Point-To-Point Links and Standard TCP/IP. (in session "POSTER Session")

The Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade (in session "POSTER Session")

The NaNet Project: Heterogeneous Real-Time Stream Processing in the Low Level Trigger of the NA62 Experiment (in session "POSTER Session")

The New Version of the LHCb SOL40_SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade (in session "POSTER Session")

The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters (in session "Systems, Planning, Installation, Commissioning and Running Experience")

The Quality Assurance of a Low-Latency, Low-Overhead, Dual-Channel Transmitter ASIC for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade (in session "POSTER Session")

The Quality Assurance Test of a VCSEL Driver ASIC for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade (in session "POSTER Session")

The SALT, a 128-Channel Readout ASIC for Upstream Tracker in the Upgraded LHCb Experiment (in session "ASIC")

The TrainBuilder Data Acquisition System for the European-XFEL (in session "POSTER Session")

The VTRx+, an Optical Link Module for Data Transmission at HL-LHC (in session "Optoelectronics and Links")

Time-to-Digital Converter with Adjustable Resolution Using a Digital Vernier Ring Oscillator (in session "POSTER Session")

Timing and Position Measurements with Ultra-Fast Silicon Detectors (in session "Other")

Trends in Radiation Effects for sub-65 nm Technologies (in session "Invited Talk")

Two High-Speed Dual-Channel VCSEL Driver (in session "POSTER Session")

Upgrade of the ATLAS Monitored Drift Tube Frontend Electronics for the HL-LHC (in session "POSTER Session")

Upgrade of the ATLAS Thin Gap Chamber Electronics for HL-LHC (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip (in session "POSTER Session")

Validation of the Front-End Electronics and Firmware for LHCb Vertex Locator. (in session "Systems, Planning, Installation, Commissioning and Running Experience")

Welcome (in session "Opening and Welcome")

Welcome to SCIPP - Research at SCIPP and at UCSC (in session "Invited Talk")

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TWEPP 2017 Topical Workshop on Electronics for Particle Physics

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