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Description
The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a sampling rate of 2 Gsps with an analogue -3 dB bandwidth of more than 400 MHz. Each channel integrates 128 sampling cells and a ramp-compare ADC. With this ASIC, sine waveform and reconstructed PMT waveform recording tests were conducted. We also evaluated its performance on fast pulse timing, and the timing precision is proved to be better than 20 ps RMS after a series of correction strategies.
Summary
In modern particle physics experiments, waveform digitization offers maximum possible information, such as arrival time, charge, waveform shape, and so on. As for fast detectors used for precise timing, e.g. Multi-gap Resistive Plate Chamber (MPRC), a high sampling rate up to Gsps (Giga-samples per second) is required. The traditional solution employing fast Analog-to-Digital Converters (ADCs) in the Gsps level suffers from power dissipation, and especially high cost. The above disadvantages preclude it from application in modern particle physics experiments, in which a huge volume of channels are often employed. An alternative approach to tackle these requirements is Switched Capacitor Arrays (SCAs). SCAs use a series of capacitors, connected via switches to an input bus to sample an analogue signal, and this architecture has the advantage that they can operate at several Gsps with low power consumption.
This paper presents a two-channel SCA ASIC prototype, and each channel has a depth of 128 sampling cells. The shared sampling clock is generated by an on-chip Delay-Locked Loop (DLL), in which the time delay of each stage is made from a CMOS current-starved inverter and the adjustable range is between 0.5 ~ 2 ns. Because of the feedback operation mode, the sampling rate is determined completely by the external input reference clock, almost independent of temperature, power supply and process. In the sampling circuit, to obtain a high input bandwidth and to reduce the distortion cause by switch’s on-resistance, a careful tradeoff is made. Finally, a dual CMOS switch and a 110 fF MOS capacitor are used. After waveform capture, parallel digital conversion of all sampled signals is done on-chip with a ramp-compare ADC which consists of a global ramping voltage, a comparator for each cell and a 12-bit Gray-code counter. The digitized data is serially read out using a shift register ‘token’ architecture.
The proposed prototype was fabricated in CMOS 180 nm technology, and it can be fully functional at the sampling rate of 2 Gsps. Results in terms on DC offset, noise, frequency response, sampling intervals correction and fast pulse timing are presented. The input voltage range is 0~1.1 V with an uncorrected Integral Non-Linearity (INL) 1% over a 900 mV dynamic range, and the offset among each cell varies between -15.62 ~ 25 mV because of process. Noise, after on-chip digitization, is equivalent to ~1.5 mV RMS. The frequency response result indicates that the analogue -3 dB bandwidth of the chip is above 400 MHz. For precision waveform timing extraction, the sampling interval variations must be calibrated and corrected. The ‘zero-crossing’ method is used to get the real sampling intervals. Finally, the effective timing resolution with a fast Gaussian input pulse is calculated by waveform feature extraction after linearity and sampling intervals correction as well as leading-edge fitting, and the timing precision of this ASIC is proved to be better than 20 ps RMS. Power consumption of the chip is about 48 mW at a 2 Gsps sampling rate.
