University of Pavia
Author in the following contributions
- Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
- Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications
- Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC
