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Description
LHCb is a dedicated experiment searching for new physics by studying CP violation and rare decays of b and c quarks. The LHCb silicon vertex detector (VELO) is a crucial component of the experiment. The detector provides precision space points close to the interaction point and thus used to reconstruct b decay vertices, in both the trigger and offline track reconstruction as well as being an important part of the tracking system. In order to match the upgraded LHCb readout system, which aims at a trigger-free read-out of the entire detector at the bunch-crossing rate of 40 MHz, all silicon modules and electronics must be replaced. The upgraded VELO will be a hybrid pixel detector (55x55 um pitch), read out by the VeloPix ASIC derived from the Timepix3. The sensors and ASICs will approach the interaction point to within 5.1 mm and be exposed to a radiation dose of up to 370 Mrad. The hottest ASICs must sustain pixel hit rates of more than 900 Mhits/s and produce an output data rate of over 15 Gbit/s, adding up to 1.6 Tbit/s of data for the whole VELO.
This paper will present an overview of the tests performed on the first version of the VeloPix, issues found and solutions. All digital and analogue functionality has been validated and conforms to specifications. Low temperature operation was verified and tests with a probecard were successful. Total Ionising Dose irradiations have been carried out with irradiation up to 400 Mrad which resulted in no change in digital power consumption and no drift in analogue parameters. Two testbeams have been carried out. One to crosscheck the synchronization, high rate capabilities and tracking performance using 5 VeloPix planes in a telescope at rates up to 300 Mtracks/s. Another one for timewalk studies using the Timepix3 telescope. Jitter on the clock that is used for the 4.8 Gbits/s serialiser generates erroneous packets, which can be reduced by adding decoupling outside of the chip and tuning the internal clock phase. Four sessions of Single Event Effects testing have been carried out in the Heavy ion facility in Louvain-la-Neuve. We found unexpected Single Event Latch-up (SEL), large cross section for the reset circuit and some small design flaws. To solve/mitigate SEE and jitter issues a second version of the VeloPix will be submitted. This poster will describe the architecture of the VeloPix chip, the test results and design changes that have been implemented.
