Indico has been upgraded to version 3.1. Details in the SSB
Mar 20 – 22, 2018
University of Washington Seattle
US/Pacific timezone

Level-1 Track Finding with all-FPGA system at CMS for the HL-LHC

Mar 20, 2018, 2:00 PM
25m
Physics-Astronomy Auditorium A118 (University of Washington Seattle)

Physics-Astronomy Auditorium A118

University of Washington Seattle

Oral 2: Real-time pattern recognition and fast tracking Session2

Speaker

Zhengcheng Tao (Cornell University (US))

Description

With the high luminosity upgrade of LHC, incorporating tracking information into the CMS Level-1 trigger becomes necessary in order to maintain a manageable trigger rate. The main challenges Level-1 track finding faces are the large data throughput from the detector at the collision rate of 40 MHz and 4 μs time budget to reconstruct charged particle tracks with sufficiently low transverse momentum to be used in Level-1 trigger decision. Dedicated all-FPGA hardware systems with time-multiplexed architecture have been developed for track finding to deal with these challenges. The algorithm and performance of the pattern recognition and particle trajectory determination are discussed in this talk. The implementation on customized boards and commercially available FPGAs are presented as well.

Primary author

Zhengcheng Tao (Cornell University (US))

Presentation materials

Peer reviewing

Paper