Speaker
Description
To exploit the physics potential of the ATLAS experiment at the HL-LHC a trigger system with a first-level trigger rate of 1 MHz at a maximum latency of 10 µs will be employed. The TDCs of the current front-end electronics of the ATLAS muon drift-tube (MDT) chambers is incompatible with these trigger requirments and will have to be replaced by new TDCs. So will have the amplifier discriminator (ASD) chips which are mounted on common front-end cards with the TDCs.
A new ASD chip with 8 eights channel was developed in 130 nm CMOS technology in Global Foundries process. The system is composed by the cascade of the analog signal processing front end and the Wilkinson A/D, performing both time-over-threshold and charge measurement. The sensitivity at the output of the analog signal processing chain is 14 mV/fC, while the equivalent-noisecharge is 0.6 fC (~3.38 ke), performing <12 ns preamplifier rise time. These performances have been achieved while managing very high detector parasitic capacitance at the front-end input (~60 pF). Each channel consumes less than 10 mA from a single 3.3-V supply voltage. In 130 nm CMOS, the total area occupancy is 6.3 mm^2.
In our presentation the results of laboraty tests with test pulses as well as results which were obtained with the new chips on a muon chamber operated in a highly energetic muon beam under varying gamma background rated in CERN's Gamma IrradiationFacilily GIF++. Thanks to a higher amplification the new chip shows a better spatial resolution than the old ASD chip currently used in the ATLAS experiment.
