24-28 June 2018
Sundsvall
Europe/Zurich timezone

A cost and energy efficient data acquisition architecture for pixel detectors in mobile applications using embedded multi-core processors

27 Jun 2018, 14:20
20m
Quality Hotel, Folkets Hus (Sundsvall)

Quality Hotel, Folkets Hus

Sundsvall

Esplanaden 29 Sundsvall, Sweden
Oral general Oral

Speaker

Oliver Keller (CERN / University of Geneva)

Description

Versatile pixel detector readout chips like the Timepix3[1] offer interesting features for various physics related applications. Since these fast chips record hit rates of up to 80 Mhits/s, available readout systems focus on ensuring data throughput at highest possible rates [2]. Typical data acquisition electronics for modern pixel detectors are therefore centred around field-programmable gate arrays (FPGA) consuming power in the order of 10 Watt and more.
For mobile applications like educational settings [3], low power consumption, a streamlined user experience and compact size is more important than the ability to detect large amounts of particle flux. This contribution elaborates on an alternative data acquisition architecture based on embedded multi-core processors, emphasizing size, cost and energy efficiency with a power consumption of 1-2 Watt on average. A silicon sensor bias supply design meeting these requirements including safety is featured as well.
The developed electronics and software is geared towards battery-powered use of Timepix3 in inquiry-based learning environments but can be also used in other mobile applications such as dosimetry. Based solely on embedded processors, this novel approach enables faster development cycles and an overall simplified system design compared to a traditional FPGA-based solution. Additional functionality such as on-board processing of pixel data can be handled by separate processor cores leading to a scalable solution. The presented architecture can be adapted for other pixel detectors as long their serial or parallel output lines can be configured to operate at speeds of 100 Mbit/s or less. Data output options are either wired or wireless Ethernet and local storage.

[1] T. Poikela et al (2014) Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout, JINST 9 C05013
[2] J. Visser et al (2015) SPIDR: a read-out system for Medipix3 & Timepix3, JINST 10 C12028
[3] O. Keller et al (2016) iPadPix - A novel educational tool to visualise radioactivity measured by a hybrid pixel detector, JINST 11 C11032

Primary author

Oliver Keller (CERN / University of Geneva)

Co-authors

Sascha Schmeling (CERN) Andreas Müller (University of Geneva) Mathieu Benoit (University of Geneva)

Presentation Materials