Speaker
Description
We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC-TOSA/ROSA. MTx+ and MTRx+ use the dual-channel VCSEL driver ASIC LOCld65, developed in a 65-nm CMOS technology and tested up to 14 Gbps. For the moment MTRx+ uses a GBTIA-embedded ROSA. The electrical connector is the same as that in SFP+. Both MTx+ and MTRx+ receive multimode LC-connectorized fibers. The module is below 6 mm in height and can be panel or board mounted. Prototype modules and measurement results are presented.
Summary
Improving on MTx and MTRx, the optical modules for the ATLAS LAr trigger upgrade, we present the MTx+ and MTRx+. The improvements are: the electrical connector is now the same as that in SFP+. The optical connector is now the standard LC connector. The transmitter data rate is now up to 14 Gbps per channel. Both modules stay below 6-mm in height. They can be panel or board mounted.
LOCld65 is a dual-channel VCSEL driver ASIC designed in a 65-nm CMOS technology. Either channel can be switched off if not in use. The channel data rate is up to 14 Gbps. Employing a full differential structure, LOCld65 consists of an input amplifier, a pre-driver, and an output amplifier. The input amplifier and the output driver each have a programmable continuous time linear equalizer (CTLE) to compensate the high-frequency signal loss. The pre-driver has four stages of limiting amplifiers. Two successive amplifiers share an inductor to improve the bandwidth and to reduce the chip area. The total gain of the limiting amplifiers is greater than 18 dB and the bandwidth is higher than 10 GHz. The bias current and the modulation current are programmable via I2C from 0.1 to 9.5 mA and from 2 to 8 mA, respectively. The die is 1 mm x 1 mm. LOCld65 is packaged in QFN24 with 0.5 mm pitch.
The module dimension is 44.5 mm (length) x 18.2 mm (width) x 5.8 mm (height). The module stays below 6 mm to meet the mechanical requirement in LAr and can be both panel and board mounted. We use two TOSAs from Truelight (Part# TTF-1F59-427). MTRx+ uses the GBTIA-embedded ROSA for the moment, before a 65-nm CMOS based TIA/LA ASIC becomes available.
Four prototype modules have been tested. At 14 Gbps, they all pass the Fiber-Channel eye mask test. The currents at 1.2 V and 3.3 V (for the VCSEL) are 67 mA and 13 mA, respectively. The total power consumption of MTx+ at 14 Gbps is 123 mW. The rise time and the fall time are 35 ps and 50 ps, respectively. A prototype chip is tested in x-rays up to 270 kGy (SiO2). During and after the test, no significant degradation was observed in eye diagram performances and in the currents of the 1.2 V and 3.3 V power. More tests on TID will be carried out. Tests on single event upset (SEE) will also be conducted.
Prototypes of the optical modules with the carrier boards for evaluations are available for system level development. They may be suitable for testing the lpGBT ASIC that is coming out soon.
