The ISOLDE facility at CERN has the largest range of radioactive beams available worldwide. Produced with the Isotope-Separation-On-Line technique, those beams allow high-precision measurements of the nuclear properties, and are as well used for research in related fields. At the Institute for Nuclear and Radiation Physics at the KU Leuven, different groups exploit the opportunities at ISOLDE...
FPGAs are key components in space equipment due to their versatility to implement digital functions. They are embarked in satellites and used in many applications; such as observing the earth, provide telecommunications and navigation services as well as to contribute to science and explore the wider Universe.
The European FPGAs for space (BRAVE, Big Reprogrammable Array for Versatile...
The Scalable Readout System (SRS) of the RD51 collaboration with the APV25 ASIC is driving R&D for gaseous detectors. Discontinuation of APV25 and demands on flexibility concerning e.g. detector capacitance and readout rate induced a replacement of the ASIC, for which the collaboration has chosen the VMM chip of the ATLAS New Small Wheel upgrade.
A prototype SRS VMM system was operated with...
A detector, equipped with 50 µm thin CMOS Pixel Sensors (CPS), is being designed for the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. MIMOSIS is being developed at IPHC aiming to meet the requirements of the MVD. The sensor is derived from the ALPIDE pixel array read-out architecture (ITS, MFT). The required radiation tolerance is significantly higher, and the required data...
The new proton timing detectors of the Totem experiment, based on Ultrafast silicon detectors installed in Roman Pots at 220 meters from the interaction point 5 at LHC, will be read out through a fast sampler chip: the SAMPIC.
The best timing resolution can be obtained only by having the waveform of the detector signal.
The challenges to integrate the chip in the Totem-CMS DAQ and control...
Real-time track reconstruction at hadron colliders is one of the most powerful tools to select interesting events from the huge background while mitigating the pile-up effect. The Fast Tracker, an upgrade to the current ATLAS trigger system, will feed the high level trigger with high quality tracks reconstructed over the entire detector at 100 kHz rate. Half of the system has been produced and...
We present designs and test results of a radiation-tolerant VCSEL array driver ASIC (VLAD14) fabricated in 65 nm CMOS technology. VLAD14 is a 4 × 14-Gbps driver with two designs implemented in four channels, delivers 2 mA bias and 5 mA modulation currents at 44 mW/ch and 52 mW/ch, respectively. Two designs have respective innovative structures at the output stage for high-speed and low-power...
Long-reach data transmission is an enabling technology for Accelerator Instrumentation at CERN. We present the development of next generation radiation-hard single-mode optical links. This new design aims to support the increasing data volume produced by the beam sensing electronics deployed along the accelerators. We present design of the new optical data link and its characterization in...
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment to determine the neutrino mass hierarchy as the main objective. The signal detection is performed by photomultipliers with readout electronics close to them. Therefore, a highly integrated analog-to-digital conversion unit with low power and large dynamic range is developed for PMT integration. To...
Development of GEM detectors showed the need of a custom readout to fully exploit the advantages of this technology. GEM detectors can be realized with various shapes, also irregular, and high number of channels. GEMINI has been specifically designed to work with Triple-GEM detectors and it integrates 16 channels to perform readout with both analog and digital signal with Time over Threshold....
The NA62 experiment at CERN SPS is aimed at measuring the branching ratio of the very rare kaon decay K+-> pi+ nu nubar.
NaNet is the reconfigurable design of a FPGA-based PCI Express Network Interface Card with processing, RDMA and GPUDirect capabilities and support for multiple link technologies.
NaNet has been employed to implement a real-time distributed processing pipeline in the low...
PACIFIC is a 64 channel mixed-signal ASIC designed for the scintillating fiber (SciFi) tracker developed for the LHCb upgrade in 2019/20. It connects without interface to the 128 channel double die SiPM arrays sensing the fibers. The analog processing begins with a current conveyor followed by a tunable fast shaper and a gated integrator. The signal is digitized with a 2bit nonlinear flash ADC...
We present a 10-Gbps 4-channel VCSEL driver with an on-chip charge pump which automatically increases the power supply voltage to ensure enough voltage headroom to the VCSEL diode operating in radiation and low-temperature environment. The charge pump efficiency is above 75%. An automatic control circuit is implemented to adjust the power supply voltage to the VCSEL. The rest of the design...
The ALICE Central Trigger Processor (CTP) will be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System (TTS) based on a Passive Optical Network (PON) system. A new universal trigger board was designed which can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON. The new trigger system and the results of the...
Demand for data communication in cloud data-centres is projected to continue to grow exponentially in the next few years.
In this presentation, we will discuss the opportunity and challenges related to silicon photonics technology as a short-reach optical interconnect platform. First, we will discuss the scaling trends and industry platform. Next, we will take a deep dive into the silicon...
Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. The RD53A prototype chip (65 nm CMOS) integrates 2 shunt-LDO (SLDO) regulators that allow providing constant voltage to each power domain (analog and digital) within a serial power chain with constant current. This paper presents a detailed analysis based on simulations and...
We present the design and performance of PSEC4A: an 8-channel, 10 GSa/s switched-capacitor array waveform sampling and digitizing ASIC, which incorporates multi-event buffering to reduce deadtime induced latency for close-in-time triggers. The PSEC4A chip uses a primary sampling array of 132 sampling capacitors that can be written to a bank of 1056 storage capacitors segmented in 8 randomly...
The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (PLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude...
This paper presents a Fast-Tracker front-end (FTfe) for small-diameter Muon Drift Tube (sMDT) detectors at future hadron colliders. The design addresses the higher background rate capability required by the sMDT detectors, which needs to be complemented by suitable front-end electronics. sMDT chambers operate at short maximum drift time and, consequently, short dead-time, maximizing the muon...
The concentrator integrated circuit (CIC) is a front-end chip for both PS and 2S modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream FE chips (either MPAs or CBCs) format and transmit it to the LpGBT unit. The design and implementation in a 65nm CMOS technology of the first prototype are presented.
Recent analog to digital converters with the successive approximation (SAR ADC) are popular for high speed, low power operation, and accuracy. SAR ADC demands a precise internal digital to analog converter (DAC) which is mostly made using capacitors. This article presents two new approaches how to design the capacitor DAC in 180 nm SOI technology. The first is 10-bit split DAC and the second...
The HRFlexToT is a 16-channel ASIC for SiPM anode readout designed for Positron Emission Tomography (PET) applications that features high dynamic range (>8 bits), high speed and low power (~3,5 mW/ch). The ASIC has been manufactured using XFAB 0,18 µm CMOS technology. Initial measurements show a linearity error below 3%. Single Photon Time Resolution (SPTR) standard deviation measurements...
FEEWAVE is an ASIC designed for Multi-gap Resistive Plate Chamber (MRPC) for good time resolution. As a highly integrated chip, the ASIC includes front-end circuit, waveform sampler, and analog-digital conversion. The chip implements Time over Threshold (TOT) function and waveform digitization. It has high speed sampling rate (5 GS/s) and high trigger rate capability (50 kHz). The ASIC is...
We present a low-noise Charge-Sensitive Amplifier (CSA) manufactured in a standard 0.35μm CMOS process. The CSA is part of an integrated sensor named Topmetal-S, with an array of which, forms a charge readout plane in a high-pressure gaseous TPC for 0νββ search. A single-ended folded cascode amplifier with a 73dB open-loop gain and 340MHz gain-bandwidth product forms the main amplification...
For the ATLAS Phase-II upgrade, a complete new all-silicon inner tracker is planned, which will be readout at higher bandwidth due to finer granularity and higher occupancy.
While both subdetectors allow the usage of the GBT protocol on the downlink path, ITk Pixel needs a different uplink protocol due to the constrains given.
This work shows how a detector specific extension of the FELIX...
High data rate requirements of the CMS Outer Tracker front-end electronics in the High-Luminosity LHC and the optimum utilization of the optical link bandwidth necessitate the development of a data aggregator ASIC; namely Concentrator IC (CIC).
To facilitate the RTL code development and to allow functional verification of the CIC ASIC in the context of the entire readout chain, a simulation...
We present the design and characterization of a high performance resistance measurement circuit fabricated in a standard 0.35μm CMOS process. The circuit implements two exposed metal electrodes in the topmost metal layer which can be deposited the sensitive thin-film. Test pulse is injected into one electrode, the other electrode is directly fed into a low noise charge sensitive amplifier with...
The design of a single particle counter for therapeutical proton beams based on Low Gain Avalanche Diodes (LGADs) optimized for very fast signals is carried on in the framework of the INFN MoveIt research project. Fast signal shaping front-end electronics is mandatory in this application in order to deal with particle rates of the order of hundreds of MHz. Two preamplifier architectures, one...
This work discusses four different algorithms for the minimization of threshold dispersion in multichannel readout circuits for pixel detectors. These algorithms, which are based on different methods (e.g. charge scans, threshold scans, etc) and differs in terms of performance and computation time, have been tested on the asynchronous front-end integrated in the CHIPIX65_FE0, a readout ASIC...
In this work an experimental high-energy radiation sensor is presented which is based on an SRAM (Static Random Access Memory). The radiation flux is measured with the memory by counting the number of Single-Event Upsets (SEUs) within one readout cycle. This monolithic sensor allows a cheap alternative to existing sensors . The SRAM has a refresh rate of 100Hz with 20480 bits. The core supply...
The lpGBT is a 10 Gbps transceiver ASIC meant to be used in High Luminosity LHC detectors.
It provides a variety of communication interfaces, including multi-mode high-speed serial interfaces, I2C, and parallel IO.
The Universal Verification Methodology had been selected to verify chips design and implementation.
This paper discusses the strategies used to verify all the chip functionalities,...
Readout electronics for modern particle imaging based identification detectors must be compact, low power, deliver acceptable timing resolution and be robust to pile-ups. The solution is to integrate full waveform sampling, analog buffering and feature extraction and digital signal processing into one single Application Specific Integrated Circuit (ASoC in the following). ASoC can be used as a...
We report on the latest developments of a silicon photonic optical transmission system based on wavelength division multiplexing (WDM) for high-speed links in detector instrumentation. The essential component is a monolithically integrated multi-wavelength transmitter based on depletion-type pn-modulators. Based on our designs, a photonic transmitter chip has been fabricated. We present...
In order to satisfy the high output bandwidth requirement imposed by the HL-LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the HL-LHC pixel detector. A CDR/PLL circuit recovers clock from the 160 Mbps incoming data, and provides high speed clock to the serializer, where the 1.28 Gbps output stream is formed. The output stage employs a...
The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the forward region of the ATLAS detector at CERN's LHC. The NSW will compose two detector technologies: Micromegas (MM) and small-strip Thin Gap Chamber (sTGC). Both detectors will be used for muon triggering at the first-level trigger and for precision tracking. Four custom-designed ASICs are...
The CLIC Tracker Detector (CLICTD) is a monolithic pixel sensor chip targeted at the tracking detector of the Compact Linear Collider (CLIC). The chip features a matrix of ${16\times128}$ cells, each cell measuring ${300\times30}$$\mu m^{2}$. The cells are segmented in the long direction in order to maintain the benefits of the small collection electrode. In the digital logic, a simultaneous...
High Voltage CMOS (HVCMOS) pixel sensor ASICs are engineered to meet the requirements of ATLAS ITk pixel barrel outer layers for LHC high luminosity upgrade. This work presents the design of HVCMOS sensor ASICs with emphasis on the readout system architecture and Digital Control Unit (DCU) design. The on-chip readout system introduces an efficient data transfer scheme from pixels to chip...
Following the necessity to replace the front-end electronics of the ATLAS Monitored Drift Tube chambers, the new MDT-ASD2 ASIC has been developed and tested. The ASD2 comes as a replacement for the original octal Amplifier/Shaper/Discriminator optimized for the MDT-chamber readout for HL-LHC. The ASIC is made in IBM 130nm CMOS technology and provides superior chip-to-chip and...
The Ethernet network is a good control interface for distributed measurement systems.
The de facto standard in HEP experiments is IPbus. The experiences from using IPbus resulted in the proposal of a new Ethernet-based control interface optimized for quick parallel configuration of multiple systems.
The system ensures reliable delivery of control commands and responses.
The minimalistic local...
A FPGA based time measurement electronics is developed for MRPC (multigap resistive plate chamber) detector in TOF (time of flight) applications. The basic structure is composed of an ultra-fast amplifier/discriminator (NINO) connected to MRPC and a dedicated FPGA based time-to-digital converter to measure TOT (Time-Over-Threshold), instead of charge. Preliminary tests show that the RMS of...
CMOS Pixel Sensors have been used in subatomic physics experiments for tracking devices. There are large quantities of hits generated by particles that coming from the detector beam background impacting tracking efficiency and reducing system bandwidth. We propose to design a CMOS pixel sensor with on-chip Artificial Neural Network (ANN) to tag and remove hits generated by background particles...
The Data Processing Boards (DPB) are the important component of the development version of the CBM readout system. Even though in the final version they will be replaced with the new Common Readout Interface (CRI) PCIe boards, they are still used for development and testing of new firmware features and for operation during the beam tests.
The paper describes the current state of the DPB...
This talk will present the results of in-situ measurements of radiaton damage for the on-detector optoelectronics for the ATLAS SemiConductor Tracker. The results come from proton-proton collisions in LHC during operation in 2016 and 2017. Both p-i-n diodes and VCSELs will be presented and compared to expectations from beam tests of identical devices before the start of LHC operation. The...
The Mu3e experiment is searching for the charged lepton flavour violating decay $\mu^{+} \to e^{+}e^{-}e^{+}$. The core elements of the detector are High Voltage Monolithic Active Pixel Sensors (HV-MAPS).
The actual status of development and testing will be presented together with the latest test version of the chip. This version, the MuPix9, takes into account the testing results of the...
High speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT -which is the evolution of the GBTx SERDES- is being designed and is foreseen to be...
Due to challenging conditions of the HL-LHC, the CMS detectors are undergoing a system-wide upgrade, and specifically the complete redesign of the end cap sub-detectors.
To reach the aimed resolution of 30 ps RMS on events timing information, a precision clock distribution system providing a readout clock with a sub 15 ps RMS jitter is necessary.
In this talk, a detailed study on the current...
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to exploit new physics beyond the Standard Model. The readout ASIC is required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us...
Time of arrival measurement using the constant discrimination technique built upon continuous switched capacitor sampling of an input waveform with a precise and high frequency clock or with a bucket-brigade-type integrated MOS analog delay line for producing a delayed version of the input signal is presented. The concepts are laid out and analyzed. The relation between the sampling or...
We present the quality assurance (QA) test of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld and a low-latency, low-overhead dual-channel transmitter ASIC LOCx2 for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test, we screen about 7200 LOCld chips and 7200 LOCx2 chips to ensure their basic functionality. All tests are automatically conducted...
The Read-Out Controller (ROC) ASIC will be used to store, de-randomize, aggregate, filter and form complex packets with the digitized data coming from the New Small Wheel (NSW) muon detectors of the ATLAS experiment. The ASIC test setup is based on a Xilinx Kintex Ultrascale FPGA evaluation board, implementing input data streams emulators and output data analyzers for functional verification...
We present the readout and data transmission of a MAPS prototype MIC4 for the R&D of the CEPC vertex detector. New data-driven readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. MIC4 contains a matrix of 128 rows by 64 columns with a pixel pitch of 25 μm. By a periphery priority encoder circuit and a data readout and framing...
The design and measurement results of two rad-hard, ultra-low power 10-bit SAR ADCs, fabricated in two CMOS 130 nm technologies, are presented. Both prototypes are fully functional achieving, in process A excellent linearity (INL, DNL < 0.3 LSB) and ENOB above 9.5 for sampling rate up to 50 MSps, and in process B a very good linearity (INL, DNL around 0.5 LSB) and ENOB around 9.2 with sampling...
In order for the CMS electromagnetic and hadronic calorimeters in the barrel region (EB, HB) to support the high-luminosity upgrade of the LHC, the off-detector electronics (Back-End) must be replaced. For EB, the new Back-End has been designed to take over functions of the legacy Front-End electronics in order to handle the required increase in the sampling frequency and the granularity of...
For the high granularity end-cap calorimeter upgrade (HGCAL) of CMS, HGCROC-V1 was submitted in July 2017. It has 32 channels with the low noise preamplifier followed by 25 ns shapers, ADC and TDCs for the charge and time measurements. A 512 deep memory stores the digitized data until the readout is performed at 320 Mb/s. A trigger path, done by summing clusters of 4 adjacent channels, gives a...
The SAMPIC chip is based on the concept of Waveform Time to Digital Converter introduced in 2013. It permits performing timing measurements with a precision of a few ps directly on detector signals. The waveforms are digitized between 1.6 and 8.2 GS/s rate over 64 samples and Time Over Threshold measurement is integrated. A set of boards and DAQ system has been developed to record data with...
A serial power scheme will be used for the new inner tracking detector for the Phase-II upgrade of the ATLAS experiment. New elements are required to operate and monitor a serially powered detector, including a detector control system (DCS), constant current sources and front-end electronics with shunt regulators.
A demonstrator for the outer barrel is built at CERN to verify the concept and...
In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called GEMROC2. Primary application of this ASIC is readout of 10×10 cm2 3-stage GEM detector, however, it can be used for readout of other types of Micro Pattern Gas Detectors.
The ASIC has been designed in 350 nm CMOS process. Its basic functionality and parameters have been evaluated using internal...
We report the design and irradiation results of a radiation-tolerant low-power 4x10 Gbps VCSEL Driver array IC in 65 nm CMOS. The driver IC consumes 130 mW at 4x10 Gbps and occupies 1.9 mm x 1.7 mm. The IC is capable of sustaining TID up to 300 Mrad and produces no errors after being irradiated with a total fluence of 2.8e15 20Mev neutrons over 36 hours. The IC is powered by 1.2 V for the...
Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML...
We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC-TOSA/ROSA. MTx+ and MTRx+ use the dual-channel VCSEL driver ASIC LOCld65, developed in a 65-nm CMOS technology and tested up to 14 Gbps. For the moment MTRx+ uses a GBTIA-embedded ROSA. The electrical connector is the same as that in SFP+. Both MTx+ and MTRx+ receive multimode LC-connectorized fibers. The module is...
The Muon-to-Central Trigger Processor Interface(MUCTPI) of the Level-1 muon trigger of the ATLAS experiment is being replaced for the LHC Run-3. The upgraded MUCTPI is implemented as an ATCA module using high-end FPGAs and high-density ribbon fibre-optic modules to integrate over 270 multi-gigabit optical inputs and outputs on a single board.
The MUCTPI also features a System-on-Chip(SoC) with...
The Silicon-Strip readout ASIC (SSA) for the pixel-strip module of the Phase II upgrades of the CMS Outer Tracker detector has been prototyped in a 65nm CMOS technology employing radiation tolerant design techniques. The SSA provides real-time primitives for the on-detector particle momentum discrimination and for the readout of the complete triggered events. This contribution will present the...
The main goals of the ATLAS New Small Wheel (NSW) upgrade are to reduce fake triggers from backgrounds hits and improve the tracking efficiency in the high rate environment at the LHC. A low-latency hardware trigger processor is being developed for the NSW in the muon spectrometer. The processor will fit candidate muon segments in the small-strip Thin Gap (sTGC) and MicroMegas (MM) chambers in...
The design and measurement results of a prototype readout ASIC for the luminosity calorimeter at future linear collider are presented. The proof-of-concept ASIC, comprising 8 channels with a variable gain front-end, a differential shaper and a 10-bit SAR ADC in each channel, was fabricated in CMOS 130~nm technology. The prototype is fully functional, achieving good linearity in a wide input...
For LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET.
An upgraded L1 Topological Processor will allow to select interesting physics events applying topological...
This work presents a novel method for solving the negative effects of charge sharing phenomenon. In contrary to the existing solutions, where the hit position is determined through additional analog signal processing, the presented approach is based on a digital algorithm, called COGITO, which finds the center of gravity of a group of pixels that received and processed fractional charges...
Serenity is an ATCA prototyping platform designed to explore alternative, novel design choices for CMS Phase-2. It uses a newly available interconnect technology from Samtec (z-ray) to mount a removable processing unit (FPGA) that should mitigate risk and provides significant flexibility in processing unit choice and connectivity. The presentation will explore the pros and cons of using an...
Unlike today when “digital turns into analog” and “analog turns into digital”, back in the late 1990s, the separation between analog and digital was unmistakable and vast. The design techniques, automation flow (or the lack of it), or even the way of designers' thinking were simply incompatible. Probably the only major area that was blurring these boundaries was a read channel for magnetic...
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme requirements, such as: 50x50 µm pixels, high rate (3 GHz/cm$^2$), unprecedented radiation levels (1 Grad), high readout speed, serial powering. As a consequence a new readout chip is required.
In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator designed in 65 nm CMOS...
In this contribution, we will present the status of the electronics system of the triple-GEM detectors for the CMS GE1/1 upgrade, which is planned for installation in 2019-2020, as well as the performance of ten prototype detectors which have been installed in CMS since 2017.
For this new CMS muon sub-detector, a new front-end chip, the VFAT3, has been designed. The VFAT3 communicates with...
The present ATLAS small wheel muon detector will be replaced with a New Small Wheel detector in 2019. The frontend electronics will be implemented in about 8000 boards including the design of 4 custom ASICs capable of driving trigger and tracking primitives to the backend trigger processor and readout system. The large number of readout channels, short time available to prepare and transmit...
A major upgrade for the ATLAS Inner Tracker at the Large Hadron Collider (LHC) is scheduled in 2026. The depleted CMOS pixel sensors on high resistivity substrates in LFoundry 150 nm technology have been proven to be promising for this upgrade. Recently two large demonstrators, one based on hybrid concept called LF-CPIX and the other based on monolithic concept called LF-MONOPIX have been...
The central building block of the Upgrade are staves and petals which host up to 14 modules per side. The incoming data is sent to the EoS and multiplexed by the lpGBT chips on 10 Gbit/s links and sent via optical transmitters (VL+) off-detector. Prototype boards have been designed, manufactured and used with the present chip versions of the GBTX /GBT-SCA chip family. This talk will summarize...
Cochlear implants are the first device to successfully restore neural function. They have instigated a popular but controversial revolution in the treatment of deafness, and they serve as a model for research in neuroscience and biomedical engineering. After a visual tour of the physiology of natural hearing the function of cochlear implants will be described in the context of electrical...
The CMS detector for LHC Phase-2 will be read out at 750 kHz for an event size of 7.5 MB. The optical links from detector front-ends are aggregated in ATCA back-end boards. A DAQ-and-Timing Hub (DTH) aggregates data streams from back-end boards over point-to-point links, provides buffering and transmission over 100Gb/s TCP/IP Ethernet links. The DTH is also responsible for distributing timing,...
The H35DEMO is a HV/HR-DMAPS large area chip fabricated in AMS 350nm HV-CMOS technology. It includes two monolithic matrices with pixels of $50\times250\mu m^2$ with analog electronics embedded in a Deep N-WELL also acting as collecting electrode.
Chips were irradiated with both protons and neutrons up to the radiation doses expected for the outermost layers of the ATLAS pixel detector at...
The nSYNC is a radiation tolerant custom ASIC, developed in UMC 130 nm technology for the readout electronics upgrade of the LHCb Muon System. The chip will be exposed, over ten years of operation, to a total dose of 130 Gy and fluence of 2 · 1012 cm−2 1MeV neutrons equivalent. We present the results of radiation tests performed at the Catana facility (INFN, LNS) with 60 MeV protons beam, up...
The readout system for triggerless High Energy Physics experiments, recently under intense development, contain an aggregation and data processing modules. They are responsible for collecting data from multiple input links, pre-processing and packaging them into containers for the event selection module located next in the readout chain.
The presented article discusses design considerations...
For developing a new generation of Resistive Plate Chamber detectors, we present here an improved tapped-delay-line Time-to-Digital Converter (TDC) for time-over-threshold (TOT) measurement, which has been implemented on a low-end, 28nm cyclone V-GT FPGA. Our proposed approaches include signal reshaping and optimized routing, as well as edge-detecting and encoding only a small segment of...
One of the challenges facing the system-level design of the ATLAS ITk Strip Detector is the understanding of the TID induced leakage current in the chosen 130nm CMOS technology. The effect of ionizing radiation on the current increase of the ABC130 readout ASIC has been studied at various different dose rates and temperatures using x-ray tubes and Co-60 sources. In addition, the efficacy of...
Coordinating firmware development among many international collaborators is becoming a very widespread problem in particle physics. Guaranteeing firmware synthesis with P&R reproducibility and assuring traceability of binary files is paramount. Our HDL managing tool tackles these issues by exploiting advanced Git features and being deeply integrated with HDL IDE, with particular attention to...
The LHC planned two phases of upgrades to improve the instantaneous luminosity. An accompanying upgrade of the readout electronics for the ATLAS detectors is planned to handle the increased trigger rates and readout data bandwidth. Due to high flexibility and short development-cycle, FPGA-based systems are increasingly popular within the high-energy physics community. We present here a...
Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to...
Considered as a back-up solution of the upgraded LHCb RICH sub-detectors, the antifuse FPGAs have been seen as a viable solution to be used in the harsh radiation environment of high energy physics and space experiments. This study is a summary of test beam results performed on a 0.15 µm CMOS antifuse device with a proton beam. We are characterizing the FPGA behavior under large TID and high...
This paper presents the results of a Single Event Upset (SEU) test with heavy ions on a shift register manufactured in a 28nm commercial CMOS technology, interesting for future upgrades for HL-LHC. Results will show the cross section curve in a Linear Energy Transfer (LET) range between 3-60 MeV∙cm^2/mg for different patterns.
The CMS Barrel Muon Track finder is a component of the Level-1 Trigger which performs track reconstruction and momentum measurement in the central region of the CMS experiment.
The current algorithm uses precalculated look-up tables to estimate the track parameters. A new approach will be presented deploying a Kalman filter algorithm that
exploits DSP resources in modern FPGAs, is prototyped...
Current existing alpha/beta counters use gas-flow detectors becasue of their low energy detection threshold compared to Passivated, Implanted, Planar Silicon (PIPS®) detectors. However, gas based systems suffer drawbacks with respect to safety and required infrastructure for the gas. The latest evolutions of the characteristics of PIPS® detectors allow to reach a lower energy threshold, that...
Single muon triggers are crucial for the physics programmes at hadron collider experiments. To keep the trigger rates reasonable low they must be highly selective.
Muon system at LHC experiments and at future colliders use two muon chamber system for triggering. Fast trigger chambers, identifying the bunch crossing and providing a course momentum estimation, and slower precision chambers, for...
We propose a novel fast track finding system capable of reconstructing four dimensional particle trajectories in real time using precise space and time information of the hits. The fast track finding device that we are proposing is based on a massively parallel algorithm to be implemented in commercial field-programmable gate array using a pipelined architecture. We will present studies of...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate. Simulation of the on-detector electronics based on a trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The read-out of the ITk pixel system will be most challenging in terms of data rate. First test of read-out concepts are performed with the ITk Pixel “demonstrator”, a system composed of several ITk-style modules with in total 120 FE-I4 read-out chips. Their read-out is...
We have developed an updated DaughterBoard design for control and readout of the upgraded ATLAS hadronic Tile Calorimeter electronics for HL-LHC. The new design migrated from two QSFPs to four SFP+ modules handling: 4×9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and 2×4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT...
Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple Modular Redundancy (TMR) with clock skew insertion, a system level redundancy technique is a common practice by designers to mitigate soft error rates. However, the optimal spacing between memory elements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASIC development under the...
The CMS Drift Tubes (DT) readout system has been upgraded during the 2017-2018 technical stop to a new uTCA-based system (uROS) to deliver the performance required by the increase of LHC luminosity. It comprises 3 uTCA crates with up to 25 boards, each processing 3 sectors from each CMS wheel. The uROS board is built around a Virtex-7 FPGA, and is able to receive 72 input links. The 240-Mbps...
CMS ECAL Phase2 Front-End(FE) card is designed to provide streaming of the data generated on the Very-Frond-End(VFE) cards to the back-end electronics. FE card will use the components developed within the VersatileLink project. It will contain four or six lpGBT ASICS with corresponding VersatileLink+ optical modules. Prototype FE card was developed to validate the clock distribution, high...
This paper proposes a 1 GHz Delay Locked Loop (DLL) which was processed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. It has a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter (TDC), and achieves an rms jitter below 800 fs. One of the improvements to this low jitter comes from the...
We present the Detector Control System (DCS) system being designed for triple-GEM detectors to be installed in 2019-2020 in the CMS muon endcaps for HL-LHC. Beginning of 2017, 10 triple-GEMs, called slice-test, have been installed for the very first time in CMS. Therefore the GEM DCS had basically to be designed from scratch. We will describe its key features (hardware and software), the main...
A trigger processor demonstrator card has been designed for the CMS Barrel Muon Trigger (BMT) upgrade at HL-LHC. A two-layer system design is foreseen for BMT. Layer-1 hosts the trigger primitive algorithms and preliminary tracking algorithms. Layer-2 hosts the main track finding algorithm, the correlation between the tracks from the muon system and the track-trigger for best possible estimate...
Considerable enhancements are foreseen for the Drift Tubes (DT) subdetector during Phase-2 CMS upgrade. The new HL-LHC CMS Trigger/DAQ requirements exceed the present capabilities of the on detector electronics (MiniCrate). Therefore, as a consequence of the higher L1A rate set by CMS, as well as MiniCrate maintainability and chamber aging mitigation arguments, all MiniCrates will be replaced...
The ATLAS Experiment will upgrade its Inner Tracking system for the High-Luminosity-LHC with an all-silicon system. The strip part will be based on individual modules, constructed by gluing the front-end hybrids directly onto the strip side of the sensors. The modules will then be glued onto a low-mass local support core with services integrated. We have constructed the first double-sided...
The High-Granularity Timing Detector (HGTD) will improve the performance of the ATLAS detector for the Phase II upgrade of the HL-LHC by providing precise timing information. The detector base unit consists of a hybrid module of a 2x4 cm$^2$ Low Gain Avalanche Detector (LGAD) bump-bonded to two ASICs and wire-bonded to a Flexible Printed Circuit (FLEX cable). The latter transmits high-speed...
The ATLAS Experiment will upgrade its tracker with an all-silicon Inner Tracker (ITk) for the HL-LHC, comprising pixel and strip detectors. The strip detector is based on silicon strip sensors, which are read out by low mass radiation-hard circuits carrying custom designed radiation-hard ASICs in 130 nm technology. The circuits are made from flexible PCB multi-layer copper polyimide...
A fast continuously sampling digitiser have been designed for acquiring the signal from LaBr3 scintillating crystals detectors. They are foreseen in the FAMU experiment, aimed at spectroscopic measurements of muonic hydrogen, possibly providing insights into proton radius puzzle. The board, named GSPS, is an FMC mezzanine which hosts two off-the-shelf sampling ADC used in interleaved timing...
We present a new kind of silicon device: a High-Voltage vertical JFET, conceived as a candidate for the High-Voltage Multiplexing switch in the ATLAS upgrade of the silicon microstrip Inner Tracker (ITk). Both n-type and p-type HV-JFETs have been successfully fabricated in the silicon processing facility of Brookhaven National Lab. Probe station measurements of un-irradiated devices show low...
Radiation-hard, compact, low-mass, hybrid GaN and CMOS integrated module DC-DC converter has been designed. The converter has an input voltage of up to 18V regulated down to an output voltage of 1.5V, with 7A maximum load current. It exhibits >70% efficiency. Discrete GaN transistors are used for the power stage, and the controller circuitry and power device drivers are integrated on a 0.35um...
The Fast Tracker(FTK) is an integral part of trigger upgrade program for
the ATLAS experiment. At LHC Run2, which started operation in June 2015
at a center-of-mass energy of 13 TeV, the peak luminosity has exceeded $2×10^{34}
cm^{−2}s^{−1}$ and the LHC produce an average of 60 simultaneous collisions.
The higher luminosity demands a more sophisticated trigger system with
increased use of...
During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out the front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). This work will present the irradiation campaigns performed on the V2, V3 and V4 prototypes of the SAMPA chip. The irradiation campaigns have been performed...
The Level-1 Data Driver Card (L1DDC) was designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. L1DDC is a high speed aggregator board capable of communicating with multiple front-end electronic boards. It collects the Level-1 data along with monitoring data and transmits them to a network interface through bidirectional and/or...
This work presents an automated solution for testing medium scale ASIC productions. Small scale prototype ASIC production are tested by hand in order to validate ASIC designs, and big scale ASIC productions are validated using industrial methods either checking directly the wafer or using specific instrumentation. Scientific experiments usually require producing thousands of ASICs that do not...
In order to save the space in the underground counting rooms during the ATLAS phase II upgrades, a project dedicated to the study of the impact of taller rack integration in the actual counting rooms was launched analyzing its cooling performance and the impact on the cooling infrastructures.
A new 63U prototype rack equipped with three ATCA shelves with open bottom to top airflow, high power...
To face the harsh environmental conditions in high energy physics, the systems have to find the right balance between high availability and fault tolerance. In response to the new failures during the runs, the graceful degradation has to be adaptive, with the minimum of impact on the data acquisition chain. To improve the Trigger Concentrator Cards, during the CMS Level-1 trigger upgrade, the...
Linear array detectors with high spatial resolution and MHz frame-rates are essential for high-rate experiments at accelerator facilities. We have developed KALYPSO, a line array detector with 1024 pixels operating at 10 Mfps. To improve the spatial resolution and sensitivity at different wavelengths, novel Si microstrip sensors have been developed with a pitch of 25 µm. Furthermore, to enable...
Time response of a Silicon Photomultiplier (SiPM) depends on some of the intrinsic parameters of the sensor. Combining multiple small SiPM instead of one with larger area will reduce detector capacitance at electronic level, which can be translated into a lower jitter, and thus better Coincidence Time Resolution (CTR) of a PET system. This work provides a framework by combining GATE and an...
The Mu2e electromagnetic calorimeter is composed of un-doped CsI crystals coupled to large area Silicon Photomultipliers (SiPMs). A custom SiPM layout consisting of 2 series of 3 6x6 mm^2 UV-extended monolithic SiPMs has been developed. So far, the production of 4000 pieces is ongoing and a detailed Quality Assurance (QA) process is being carried out on each monolithic SiPMs with an...
The Ring Imaging Cherenkov detectors are key components for particle identification in LHCb experiment at CERN. The present RICH photodetectors will be replaced by multi‐anode photomultiplier tubes and front‐end electronics capable of operating at a 40MHz input rate. About 33.000 CLARO8 packaged ASICs have been manufactured and tested on a dedicated automatic pick‐and‐place station. About 4200...
The readout board for the ALICE TOF detector named DRM2 is now in the production phase: 88 boards are being produced (72 are needed in the experiment). Since the board will operate in a radiation environment (0.13 krad total dose expected in 10 years), a complete irradiation campaign at the component level was performed. We will focus on the Microsemi Igloo2 FPGA and two Avago optical...
Vacuum in the ARCs of the LHC is crucial to minimize beam – gas interactions and to assure thermal insulation of cryostats and helium distribution lines. Several hundred of sensors with their associated conditioning electronics are installed across the ARCs for both beam and insulation vacuum measurements. Simulations predict that radiation levels will greatly increase during HL-LHC era....
Real-time track reconstruction in high energy physics experiments at colliders running at high luminosity is very challenging for trigger systems. To perform pattern-recognition and track fitting, artificial Retina or Hough transformation algorithms have been introduced in the field which have usually to be implemented in the state of the art FPGA devices. In this paper we report on simulated...
The CMS experiment implements a sophisticated two-level triggering system composed of hardware-based Level-1, and a software-based High Level Trigger. A new Level-1 trigger architecture improves the performance at high luminosity experienced during Run II. The upgraded muon trigger combines information from the three muon detectors - Cathode Strip Chambers (CSC), Drift Tubes (DT) and Resistive...
The CMS ECAL barrel electronics will be upgraded for the HL-LHC to comply with increased latency and bandwidth requirements of the Level 1 trigger, to preserve detector performance despite the increased instantaneous luminosity, and to provide a precision timing measurement in addition to energy. The chosen solution includes a custom dual gain trans-impedance amplifier implemented in a 130nm...
The Embedded Local Monitor Board (ELMB) is a microcontroller based plug-in module with CANopen communication protocol. It has been widely used in LHC systems and experiments for slow-control and monitoring purposes, providing multiple galvanically isolated analog and digital inputs and outputs.
While these modules have shown excellent performance in the past 15 years, a replacement is...
The second generation of the 8 channel PaDiWa-AMPS front-end board was recently assembled at the GSI department for Experiment Electronics (GSI EE). The board implements precise TDC and QDC measurements optimized to read out the 978 PMTs of the HADES electromagnetic calorimeter (ECAL). The HADES ECAL detector is currently under commissioning. In this contribution the read-out scheme of the...
The ATLAS experiment at the LHC is undergoing a major upgrade to handle the higher collision rate that will be provided by the High-Luminosity LHC. A major component of the ATLAS Phase-II upgrade is the Inner Tracker, an all-silicon detector featuring novel n+-in-p microstrip sensors. Miniature sensors implementing this design are tested for their radiation tolerance at the upgraded...
The WaveCatcher systems are a family of powerful and low cost digitizers. Their number of channels ranges between 2 and 64. They easily replace oscilloscopes in numerous applications. They are based on the SAMLONG ASIC which samples the signal between 400 MS/s and 3.2 GS/s over 12 bits with a bandwidth of 500 MHz.
The systems can also be used as TDCs for high precision time measurement....
To maintain high trigger efficiencies and stable rates during significant changes to beam conditions throughout 2017, the CMS Level-1 calorimeter trigger required dynamic and flexible operation. Successfully running since 2015, utilising Xilinx Virtex 7 690 FPGAs and 10 Gbps optical links, the versatile design has enabled quick adaption to improve algorithms to mitigate large rates from high...
The upgrade of the ATLAS tracking detector for the HL-LHC requires radiation hard silicon sensor technologies. For the development of depleted CMOS sensor for ATLAS we combined small electrodes with minimal capacitance and advanced processing to achieve radiation hard CMOS for the ITK. We developed and tested a first full-size depleted CMOS sensor based on a 180nm imaging process. The...
Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the...
The silicon modules of the Phase-2 CMS Outer Tracker feature service hybrids, which are flex PCBs that will carry radiation-tolerant DC-DC converters, the Low Power GBT chip, and a VTRx+ module. The strip modules are powered via a two-step DC-DC conversion scheme, while the data from the front-end hybrids are collected and serialized by the LpGBT, and passed on to the VTRx, which performs...
Miromico AG has been developing high-performance I/O's in CMOS technologies for almost 15 years. The application span includes various chip-to-chip communication links, where the ICs are either sitting on the same PCB (C2C) or on different PCBs connected through a backplane (BP).
With the exponential growth of on-chip functionality and high cost of IC pads and interconnections, parallel data...
