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The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.
LHC experiments (and their operational experience) will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.
Official Web site for local information and registration
The purpose of the workshop is :
- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities
- to review the status of electronics for the LHC experiments
- to identify and encourage common efforts for the development of electronics
- to promote information exchange and collaboration in the relevant engineering and physics communities.
Registration to the workshop and local organisation information are available on:
Organised by KU Leuven with support from CERN.
The ISOLDE facility at CERN has the largest range of radioactive beams available worldwide. Produced with the Isotope-Separation-On-Line technique, those beams allow high-precision measurements of the nuclear properties, and are as well used for research in related fields. At the Institute for Nuclear and Radiation Physics at the KU Leuven, different groups exploit the opportunities at ISOLDE in a number of activities. Nuclear structure is studied using laser spectroscopy, decay and reaction methods, with a focus on the new phenomena appearing in system far from stability. Properties of the fundamental interactions are investigated through precision measurements of the nuclear beta-decay. Solid-state physicists use the ISOLDE radioactive ions as probes of bulk and 2D-materials. Finally, the proton beam of the PS-Booster is used at MEDICIS to research innovative isotopes for medical application. This talk will give an overview of these activities.
FPGAs are key components in space equipment due to their versatility to implement digital functions. They are embarked in satellites and used in many applications; such as observing the earth, provide telecommunications and navigation services as well as to contribute to science and explore the wider Universe.
The European FPGAs for space (BRAVE, Big Reprogrammable Array for Versatile Environtments) is a family of reprogrammable FPGAs that are radiation hardened to withstand the radiation requirements for most space missions. This talk provides an overview of the BRAVE FPGAs, with a technical overview of the architecture capabilities as well as a summary the radiation test results for the NG-MEDIUM, the first member of the family.
ASML is an important player in the semiconductor industry. Using lithography, small structures are being written on wafers resulting in the active devices as we know them from servers, PCs and mobile phones.
In my talk I will sketch the technological challenges which ASML faces mechanical, electronical, and optical and sketch the progress over the last 30 years. The talk concentrates on the upcoming technology where EUV (extreme ultraviolet light at 13.5 nm) is being used for lithography.
The first prototype of the full-size, full-functionality Macro Pixel ASIC has been prototyped in a $65\,nm$ technology employing radiation tolerant techniques. It is a pixel readout ASIC designed for the Phase-II upgrade of the CMS Outer Tracker detector. It features novel on-chip particle discrimination capabilities allowing performing real-time event-driven readout of high transverse momentum particles at a $40\,MHz$ rate. This data flow is complemented with a triggered and zero suppressed readout data path for the readout of full events at a maximum rate of $1\,MHz$. This contribution presents the functional and performance evaluation results obtained from silicon prototypes.
A detector, equipped with 50 µm thin CMOS Pixel Sensors (CPS), is being designed for the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. MIMOSIS is being developed at IPHC aiming to meet the requirements of the MVD. The sensor is derived from the ALPIDE pixel array read-out architecture (ITS, MFT). The required radiation tolerance is significantly higher, and the required data throughput is 3 times higher than ALPIDE. Thus, a fully revisited digital circuitry was designed to fulfil the requirements. This paper will show the tests results and describes the next step of the development at IPHC.
We present designs and test results of a radiation-tolerant VCSEL array driver ASIC (VLAD14) fabricated in 65 nm CMOS technology. VLAD14 is a 4 × 14-Gbps driver with two designs implemented in four channels, delivers 2 mA bias and 5 mA modulation currents at 44 mW/ch and 52 mW/ch, respectively. Two designs have respective innovative structures at the output stage for high-speed and low-power operations. Widely-open optical eye diagrams at 14 Gbps have been captured for both two designs. Full channel optical test and radiation test will be carried out and reported at the workshop.
The Scalable Readout System (SRS) of the RD51 collaboration with the APV25 ASIC is driving R&D for gaseous detectors. Discontinuation of APV25 and demands on flexibility concerning e.g. detector capacitance and readout rate induced a replacement of the ASIC, for which the collaboration has chosen the VMM chip of the ATLAS New Small Wheel upgrade.
A prototype SRS VMM system was operated with small GEM detectors at test beams and hardware components are finalised. More than twelve groups signed as primary system users.
The readout chain and implementation of the VMM in SRS is outlined with applications and further developments.
The new proton timing detectors of the Totem experiment, based on Ultrafast silicon detectors installed in Roman Pots at 220 meters from the interaction point 5 at LHC, will be read out through a fast sampler chip: the SAMPIC.
The best timing resolution can be obtained only by having the waveform of the detector signal.
The challenges to integrate the chip in the Totem-CMS DAQ and control systems will be discussed, and the adopted solutions reported. The system is under commissioning and will collect physics data during a special LHC run in late June. The latest results will be shown.
Real-time track reconstruction at hadron colliders is one of the most powerful tools to select interesting events from the huge background while mitigating the pile-up effect. The Fast Tracker, an upgrade to the current ATLAS trigger system, will feed the high level trigger with high quality tracks reconstructed over the entire detector at 100 kHz rate. Half of the system has been produced and integration in ATLAS is proceeding in order to demonstrate functionality with real data with a partial detector coverage. The performance of the system from tests with real data and laboratory measurements will be reviewed.
Calorimetry in high-energy physics is rapidly evolving, with new challenges and a wide variety of technologies being employed, both for signal creation and detection. Advances in large-area highly-segmented detectors are providing possibilities for high-granularity calorimetry. The CMS HGCAL, being designed to replace the existing CMS endcap calorimeters for the HL-LHC era, is one example. It is a sampling calorimeter, featuring unprecedented transverse and longitudinal readout segmentation for both electromagnetic (CE-E) and hadronic (CE-H) compartments. This will facilitate particle-flow calorimetry, where the fine structure of showers can be measured and used to enhance pileup rejection and particle identification, whilst still achieving good energy resolution. The CE-E and a large fraction of CE-H will use hexagonal silicon sensors as active detector material. The lower-radiation environment will be instrumented with scintillator tiles with on-tile SiPM readout. These concepts borrow heavily from designs produced by the CALICE collaboration but the design of such a detector at a hadron collider is considerably more challenging than at the linear colliders. This is particularly true for the electronics systems, both on- and off-detector, with low noise and power, coupled with high dynamic range, bandwidth and resistance to radiation, being just some of the specifications. We present an overview of HGCAL with some focus on the electronics systems.
Silicon photonics modulators are being investigated for use in optical links for High Energy Physics experiments. In order to withstand the harsh environment in experiments beyond the Large Hadron Collider at CERN, components will have to be resistant against extreme levels of radiation. We show that modulators, which lost their functionality after irradiation, can be fully recovered by applying a forward bias. Furthermore, it is presented that by applying a forward bias during irradiation, the irradiation-induced degradation can be compensated. The possibility of device recovery could lead to a tremendous increase of radiation resistance of the optical links.
Long-reach data transmission is an enabling technology for Accelerator Instrumentation at CERN. We present the development of next generation radiation-hard single-mode optical links. This new design aims to support the increasing data volume produced by the beam sensing electronics deployed along the accelerators. We present design of the new optical data link and its characterization in terms of functional performance and radiation tolerance.
High Density Interconnect (HDI) hybrids are being developed for the CMS Tracker Phase Two Upgrade for the HL-LHC. These hybrids are carbon fibre reinforced flexible circuits with flip-chips, passives and connectors. Their operational lifetime is determined by the reliability of the solder joints of the surface mount components (flip-chips, passives, connectors) and the copper traces and vias in the hybrid substrate. Specific test coupons were exposed to accelerated thermal stress cycles, aiming to test the reliability of the solder joints, vias and traces. Results from different suppliers and technologies will be evaluated and compared.
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground experiment to determine the neutrino mass hierarchy as the main objective. The signal detection is performed by photomultipliers with readout electronics close to them. Therefore, a highly integrated analog-to-digital conversion unit with low power and large dynamic range is developed for PMT integration. To achieve the resulting need for a low failure rate a new test strategy is proposed. Various methods to increase the test coverage, which are implemented in the chip are presented. Also, appended features and measurement results from the second generation of the readout chip are presented.
Development of GEM detectors showed the need of a custom readout to fully exploit the advantages of this technology. GEM detectors can be realized with various shapes, also irregular, and high number of channels. GEMINI has been specifically designed to work with Triple-GEM detectors and it integrates 16 channels to perform readout with both analog and digital signal with Time over Threshold. GEMINI also allows to set a different threshold for every channel to compensate channel inhomogeneity. This work compares simulations with lab measurements and presents results of the imaging of an X-ray source performed with GEMINI.
PACIFIC is a 64 channel mixed-signal ASIC designed for the scintillating fiber (SciFi) tracker developed for the LHCb upgrade in 2019/20. It connects without interface to the 128 channel double die SiPM arrays sensing the fibers. The analog processing begins with a current conveyor followed by a tunable fast shaper and a gated integrator. The signal is digitized with a 2bit nonlinear flash ADC operating at 40MHz. The results of every two channels are serialized and transmitted at 320MSa/s over a differential SLVS data link. PACIFIC has been designed using a 130nm CMOS technology and power consumption kept below 10mW/channel.
We present a 10-Gbps 4-channel VCSEL driver with an on-chip charge pump which automatically increases the power supply voltage to ensure enough voltage headroom to the VCSEL diode operating in radiation and low-temperature environment. The charge pump efficiency is above 75%. An automatic control circuit is implemented to adjust the power supply voltage to the VCSEL. The rest of the design is based on an earlier prototype VLAD14, and will be fabricated with a 65 nm CMOS process in mid -May.
The detector module of the Silicon Tracking System (STS) of the Compressed Baryonic Matter (CBM) experiment at FAIR (GSI) consists of double-sided silicon microstrip sensors with a size up to 124 mm x 62 mm which are connected to the read-out electronics by flexible microcables. The production of the detector modules faces several challenges. A new multilayer copper microcable with low material budget has been designed to achieve low mass and low capacitance up to 50 cm length. We present the detector production method based on novel high-density gold-stud bump-bonding technology of silicon die on microcable.
The NA62 experiment at CERN SPS is aimed at measuring the branching ratio of the very rare kaon decay K+-> pi+ nu nubar.
NaNet is the reconfigurable design of a FPGA-based PCI Express Network Interface Card with processing, RDMA and GPUDirect capabilities and support for multiple link technologies.
NaNet has been employed to implement a real-time distributed processing pipeline in the low level trigger of the experiment, operating on the data streams produced by the RICH detector with an orchestrated combination of heterogeneous computing devices (CPUs, FPGAs and GPUs).
Recent results collected during NA62 runs are presented and discussed.
The ALICE Central Trigger Processor (CTP) will be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System (TTS) based on a Passive Optical Network (PON) system. A new universal trigger board was designed which can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON. The new trigger system and the results of the tests and verification of the first 23 boards, produced at the beginning of 2018, will be presented.
Demand for data communication in cloud data-centres is projected to continue to grow exponentially in the next few years.
In this presentation, we will discuss the opportunity and challenges related to silicon photonics technology as a short-reach optical interconnect platform. First, we will discuss the scaling trends and industry platform. Next, we will take a deep dive into the silicon photonics roadmap, covering both passive and high-speed active optical devices. We will describe how these building blocks can be combined to implement low-power Terabit-scale optical transceivers. Finally, we will present other opportunities for silicon photonics outside datacom.
Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. The RD53A prototype chip (65 nm CMOS) integrates 2 shunt-LDO (SLDO) regulators that allow providing constant voltage to each power domain (analog and digital) within a serial power chain with constant current. This paper presents a detailed analysis based on simulations and measurements of the RD53A chip behavior at system level. SLDO performance, system transient behavior (start-up, load changes, parasitic components implications) as well as noise studies are shown.
In this work an experimental high-energy radiation sensor is presented which is based on an SRAM (Static Random Access Memory). The radiation flux is measured with the memory by counting the number of Single-Event Upsets (SEUs) within one readout cycle. This monolithic sensor allows a cheap alternative to existing sensors . The SRAM has a refresh rate of 100Hz with 20480 bits. The core supply voltage of the memory can be lowered to increase the SEU sensitivity. The sensor was verified experimentally with heavy ions, protons and two-photon laser tests.
The concentrator integrated circuit (CIC) is a front-end chip for both PS and 2S modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream FE chips (either MPAs or CBCs) format and transmit it to the LpGBT unit. The design and implementation in a 65nm CMOS technology of the first prototype are presented.
In order to satisfy the high output bandwidth requirement imposed by the HL-LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the HL-LHC pixel detector. A CDR/PLL circuit recovers clock from the 160 Mbps incoming data, and provides high speed clock to the serializer, where the 1.28 Gbps output stream is formed. The output stage employs a three-tap current-mode logic driver with adjustable tap coefficient for optimal pre-emphasis. Each RD53A chip includes four output lanes, offering in total 5.12 Gbps output bandwidth. The circuit topology as well as measurement results will be presented.
High data rate requirements of the CMS Outer Tracker front-end electronics in the High-Luminosity LHC and the optimum utilization of the optical link bandwidth necessitate the development of a data aggregator ASIC; namely Concentrator IC (CIC).
To facilitate the RTL code development and to allow functional verification of the CIC ASIC in the context of the entire readout chain, a simulation framework was built incorporating all front-end ASICs; Macro Pixel ASIC (MPA) and Short Strip ASIC (SSA) for Pixel-Strip (PS) modules and CMS Binary Chip (CBC) for Strip-Strip (2S) modules.
We present the design and performance of PSEC4A: an 8-channel, 10 GSa/s switched-capacitor array waveform sampling and digitizing ASIC, which incorporates multi-event buffering to reduce deadtime induced latency for close-in-time triggers. The PSEC4A chip uses a primary sampling array of 132 sampling capacitors that can be written to a bank of 1056 storage capacitors segmented in 8 randomly accessible blocks. Each channel has an integrated 11-bit ramp-compare ADC with shift-register readout that permits simultaneous sampling and readout operations. The relatively short primary sampling array allows an analog bandwidth of the input greater than 1.5 GHz.
The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (PLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude information. Starting from a 40 MHz input clock, the PLL provides output clocks of 160 MHz and 320 MHz with a phase resolution of 11.25° and 22.5°, respectively. The prototype, integrated in 130 nm CMOS technology, has 0.02mm2 of area and 1.2V of supply voltage.
This paper presents a Fast-Tracker front-end (FTfe) for small-diameter Muon Drift Tube (sMDT) detectors at future hadron colliders. The design addresses the higher background rate capability required by the sMDT detectors, which needs to be complemented by suitable front-end electronics. sMDT chambers operate at short maximum drift time and, consequently, short dead-time, maximizing the muon detection efficiency. FTfe ensures fast baseline restoration with a reset interval of maximum 160ns, such that muon pulses are not distorted or even masked by preceding background pulses. The device has been designed in 1V-28nm-CMOS technology with 0.03mm2 of area, 4.7mV/fC sensitivity and 0.24fC ENC.
Recent analog to digital converters with the successive approximation (SAR ADC) are popular for high speed, low power operation, and accuracy. SAR ADC demands a precise internal digital to analog converter (DAC) which is mostly made using capacitors. This article presents two new approaches how to design the capacitor DAC in 180 nm SOI technology. The first is 10-bit split DAC and the second is 8-bit binary-scaled DAC. Layout styles for each of capacitor DAC are shown. Simulations confirm that both of capacitor array have nonlinearities under the magnitude of the least significant bit without a calibration scheme.
The HRFlexToT is a 16-channel ASIC for SiPM anode readout designed for Positron Emission Tomography (PET) applications that features high dynamic range (>8 bits), high speed and low power (~3,5 mW/ch). The ASIC has been manufactured using XFAB 0,18 µm CMOS technology. Initial measurements show a linearity error below 3%. Single Photon Time Resolution (SPTR) standard deviation measurements performed using a Hamamatsu LCT4 MPPC (3x3 mm2, 75 µm cell) shows 40% improvement with respect to the previous version of the ASIC, setting this specification in the order of 60 ps and reducing 3 times power consumption.
FEEWAVE is an ASIC designed for Multi-gap Resistive Plate Chamber (MRPC) for good time resolution. As a highly integrated chip, the ASIC includes front-end circuit, waveform sampler, and analog-digital conversion. The chip implements Time over Threshold (TOT) function and waveform digitization. It has high speed sampling rate (5 GS/s) and high trigger rate capability (50 kHz). The ASIC is fabricated with 0.18 um CMOS technology. In this paper, the design details of the chip will be given.
We present a low-noise Charge-Sensitive Amplifier (CSA) manufactured in a standard 0.35μm CMOS process. The CSA is part of an integrated sensor named Topmetal-S, with an array of which, forms a charge readout plane in a high-pressure gaseous TPC for 0νββ search. A single-ended folded cascode amplifier with a 73dB open-loop gain and 340MHz gain-bandwidth product forms the main amplification stage in this CSA. Measurements show that the conversion gain of the CSA with a 3fF feedback capacitor is 168mV/fC. The equivalent noise charge of the CSA after a trapezoidal pulse shaper is 28.7e- rms with a 5pF detector capacitance.
A pixel chip based on the Hit-Driven scheme was designed for the HEPS project in China. The full information of every photon, including the hit position, arrival time, and photon energy, are detected by the ToT method. Thus a 3D animation of clusters can be rebuild. Priority arbitrary logic was designed to readout all the hit pixels sequentially to the column FIFO, and the chip overall buffer. The beamline gate signal was used for trigger to make the level 1 data selection. A full functional chip was taped out and proved. It also survived after 100 Mrad X-ray irradiation.
We present a high resolution sigma-delta ($\Sigma\Delta$) Analog-to-Digital Converter (ADC) manufactured in a 0.35 $\mu$m CMOS process. The ADC consists of a cascaded $\Sigma\Delta$ modulator and a SINC4 decimation filter. Tests show that the ADC achieved a 80 dB signal-to-noise ratio and a 14 effective number of bits with a 25.6 MHz sampling clock at a 200 kHz input signal. Its characteristics are uniquely suited for high-pressure TPC readout that focuses on high energy resolution.
We present the design and characterization of a high performance resistance measurement circuit fabricated in a standard 0.35μm CMOS process. The circuit implements two exposed metal electrodes in the topmost metal layer which can be deposited the sensitive thin-film. Test pulse is injected into one electrode, the other electrode is directly fed into a low noise charge sensitive amplifier with selective feedback capacitor. Simulations and initial tests show that the circuit achieved a 100ῼ~100Tῼ measuring range and a 10ῼ resolution. These characteristics enable its use as the accurate resistance monitoring sensor device in future thin-film sensitive gas detection applications.
The design of a single particle counter for therapeutical proton beams based on Low Gain Avalanche Diodes (LGADs) optimized for very fast signals is carried on in the framework of the INFN MoveIt research project. Fast signal shaping front-end electronics is mandatory in this application in order to deal with particle rates of the order of hundreds of MHz. Two preamplifier architectures, one based on a fast Charge Sensitive Amplifier with self-reset capabilities and a second one based on a Trans-Impedance Amplifier have been developed in a commercial CMOS 0.11 $\rm\mu m$ technology and submitted to the foundry.
This work discusses four different algorithms for the minimization of threshold dispersion in multichannel readout circuits for pixel detectors. These algorithms, which are based on different methods (e.g. charge scans, threshold scans, etc) and differs in terms of performance and computation time, have been tested on the asynchronous front-end integrated in the CHIPIX65_FE0, a readout ASIC prototype designed in a 65nm CMOS technology.
With future pixel ASICs trending towards mega-frame rate readout, the development of ultra-high-speed readout systems is increasingly important. Here we present an ultra-fast readout system developed to operate at 10Gb/s, and intended to surpass a more conventional highly-parallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles and serialises the parallel input data in accordance with the Aurora 64b66b protocol, and transmits the data off-chip through a Current Mode Logic (CML) line-driver at 10Gb/s. A prototype is under evaluation having been fabricated in early 2018 on a 65nm Multi-Project Wafer. The results from testing are reported.
The lpGBT is a 10 Gbps transceiver ASIC meant to be used in High Luminosity LHC detectors.
It provides a variety of communication interfaces, including multi-mode high-speed serial interfaces, I2C, and parallel IO.
The Universal Verification Methodology had been selected to verify chips design and implementation.
This paper discusses the strategies used to verify all the chip functionalities, including not standard serial interfaces.
Moreover, structures of the developed UVM test benches together with performance metrics are presented.
This work describes several applications where an 8-channel enhanced Multiple Use SiPM Integrated Circuit (eMUSIC) ASIC for SiPM readout can be used to replace PMTs. Several SHiP (Search For Hidden Particles) Experiment Detectors at CERN SPS (Super Proton Synchrotron) are studying the employment of eMUSIC for the ToF (Time-of-Flight) Timing Detector with timing resolution around 100 ps. Moreover, eMUSIC is being used as a Beam loss Loss Monitor (BLM) for ALBA Synchrotron using scintillator fibers in order to capture variations in rate during the operation of the accelerator with 20 cm spacing resolution.
Readout electronics for modern particle imaging based identification detectors must be compact, low power, deliver acceptable timing resolution and be robust to pile-ups. The solution is to integrate full waveform sampling, analog buffering and feature extraction and digital signal processing into one single Application Specific Integrated Circuit (ASoC in the following). ASoC can be used as a building block for such readout devices. The prototype fabricated ASoC has 4 channels, operates at 3 GSa/s and has on-chip trigger timestamping, calibration and signal processing capabilities. ASoC also provides 8k storage samples per channel which makes it suitable for large experiments.
The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the forward region of the ATLAS detector at CERN's LHC. The NSW will compose two detector technologies: Micromegas (MM) and small-strip Thin Gap Chamber (sTGC). Both detectors will be used for muon triggering at the first-level trigger and for precision tracking. Four custom-designed ASICs are needed: one to amplify/shape/discriminate raw detector signals, two to handle the trigger signals from MM and sTGC separately, and the fourth one to readout precision data. We will present the design and current status of all ASIC prototypes.
The CLIC Tracker Detector (CLICTD) is a monolithic pixel sensor chip targeted at the tracking detector of the Compact Linear Collider (CLIC). The chip features a matrix of ${16\times128}$ cells, each cell measuring ${300\times30}$$\mu m^{2}$. The cells are segmented in the long direction in order to maintain the benefits of the small collection electrode. In the digital logic, a simultaneous $8$-bit Time of Arrival and $5$-bit Time over Threshold measurement is performed. The TowerJazz $180$nm HR-CMOS Imaging Process was selected to fulfil the requirements of the CLIC silicon tracker. In this document the CLICTD design and chip interface are presented.
High Voltage CMOS (HVCMOS) pixel sensor ASICs are engineered to meet the requirements of ATLAS ITk pixel barrel outer layers for LHC high luminosity upgrade. This work presents the design of HVCMOS sensor ASICs with emphasis on the readout system architecture and Digital Control Unit (DCU) design. The on-chip readout system introduces an efficient data transfer scheme from pixels to chip periphery. The data links work at a rate of 1.6Gbps which has been achieved by a novel serializer scheme. The test beam results on a large area AMS 0.18µm prototype without triggered readout shows more than 99% readout efficiency.
Following the necessity to replace the front-end electronics of the ATLAS Monitored Drift Tube chambers, the new MDT-ASD2 ASIC has been developed and tested. The ASD2 comes as a replacement for the original octal Amplifier/Shaper/Discriminator optimized for the MDT-chamber readout for HL-LHC. The ASIC is made in IBM 130nm CMOS technology and provides superior chip-to-chip and channel-to-channel uniformity among functional parameters, e.g. peaking time, channel gain, discriminator threshold and channel dead-time. The paper presents the general design strategy, simulation and lab test results, off and on-chamber, as well as test beam data taken at CERN with and without gamma irradiation.
The Mu3e experiment is searching for the charged lepton flavour violating decay $\mu^{+} \to e^{+}e^{-}e^{+}$. The core elements of the detector are High Voltage Monolithic Active Pixel Sensors (HV-MAPS).
The actual status of development and testing will be presented together with the latest test version of the chip. This version, the MuPix9, takes into account the testing results of the large-scale prototype MuPix8.
Design aspects such as serial powering and first measurement results on the MuPix9 will be shown.
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to exploit new physics beyond the Standard Model. The readout ASIC is required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us with 5 ns time resolution. In order to satisfy the experimental requirements, a new prototype ASIC was designed with 180 nm CMOS. The design and performance of the ASIC will be discussed.
Time of arrival measurement using the constant discrimination technique built upon continuous switched capacitor sampling of an input waveform with a precise and high frequency clock or with a bucket-brigade-type integrated MOS analog delay line for producing a delayed version of the input signal is presented. The concepts are laid out and analyzed. The relation between the sampling or shifting time interval, degree of low pass filtering of the sampled and delayed waveform, DC-level restoration and obtainable time of arrival measurement precision as well as studies of power consumption and implementation as an integrated circuit block are reviewed.
We present the quality assurance (QA) test of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld and a low-latency, low-overhead dual-channel transmitter ASIC LOCx2 for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test, we screen about 7200 LOCld chips and 7200 LOCx2 chips to ensure their basic functionality. All tests are automatically conducted and controlled by LabVIEW software running on computers. The QA test systems and test results for the two ASICs are reported.
The Read-Out Controller (ROC) ASIC will be used to store, de-randomize, aggregate, filter and form complex packets with the digitized data coming from the New Small Wheel (NSW) muon detectors of the ATLAS experiment. The ASIC test setup is based on a Xilinx Kintex Ultrascale FPGA evaluation board, implementing input data streams emulators and output data analyzers for functional verification which are controlled and monitored by a MicroBlaze microprocessor. Jitter and skew of the ASIC’s PLL outputs are measured using the FPGA transceiver eye-margining circuits. The design validation, test procedure and quality-assurance mass-testing results are presented.
We present the readout and data transmission of a MAPS prototype MIC4 for the R&D of the CEPC vertex detector. New data-driven readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. MIC4 contains a matrix of 128 rows by 64 columns with a pixel pitch of 25 μm. By a periphery priority encoder circuit and a data readout and framing circuit, MIC4 readouts data real time without on-chip memory. An 8B10B encoder, a 10:1 serializer, and an LVDS driver are implemented to transmit serially the data at 1.2 Gbps.
Commercial-off-the-shelf photonic components do
not satisfy the requirements of typical spacecraft or particle-physics detector applications. In order to reduce
costs and schedule risk for insertion of photonic components into these harsh-environment applications,
we developed single- and multi-channel ruggedized photonic transceiver modules and active optical
cables for aerospace, particle physics detectors and other harsh-environment fiber-optic datalink
applications operating at up to 12.5 Gbps per lane.
In this presentation we will review performance characteristics and results of reliability,
environmental and radiation tests including gamma, neutron, proton and heavy ions, for these transceiver
components.
Due to challenging conditions of the HL-LHC, the CMS detectors are undergoing a system-wide upgrade, and specifically the complete redesign of the end cap sub-detectors.
To reach the aimed resolution of 30 ps RMS on events timing information, a precision clock distribution system providing a readout clock with a sub 15 ps RMS jitter is necessary.
In this talk, a detailed study on the current technologies as well as an extensive discussion of the R&D dedicated to the low-jitter clock distribution studies are presented.
The miniaturised optical transceiver module, developed in the framework of the Versatile Link PLUS project (VL+) will be installed in the upgraded detector front-ends at the HL-LHC. The modules will have to operate over a wide temperature range (-35 °C to +60 °C). We describe the impact of the temperature on the performance of the transceiver and we present simulation and measurement results obtained during the thermal characterisation of different transceiver prototypes.
High speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT -which is the evolution of the GBTx SERDES- is being designed and is foreseen to be installed in CMS and ATLAS for Phase-2 upgrades. The LpGBT-FPGA IP core is proposed to offer a backend counterpart of the LpGBT. This paper presents the status of its development, the IP architecture and the future steps.
This talk will present the results of in-situ measurements of radiaton damage for the on-detector optoelectronics for the ATLAS SemiConductor Tracker. The results come from proton-proton collisions in LHC during operation in 2016 and 2017. Both p-i-n diodes and VCSELs will be presented and compared to expectations from beam tests of identical devices before the start of LHC operation. The VCSELs show clear evidence for radiation damage, as expected qualitatively from earlier studies. However the p-i-n diodes do show significant radiation damage. There is strong evidence for an unexpected rate-dependent effect for the p-i-n diodes.
We report on the latest developments of a silicon photonic optical transmission system based on wavelength division multiplexing (WDM) for high-speed links in detector instrumentation. The essential component is a monolithically integrated multi-wavelength transmitter based on depletion-type pn-modulators. Based on our designs, a photonic transmitter chip has been fabricated. We present experimental results of its components such as modulators, (de-)multiplexers and power couplers and discuss the development process starting from the concept and the component design through to simulations and experimental results. With this chip, all building blocks are available for building a link demonstrator.
The strategy for beam setup and machine protection of the accelerators at the European Organization for Nuclear Research (CERN) relies strongly on their Beam Loss Monitoring (BLM) systems, which are currently being renovated. The main acquisition path has shown very promising results, and development is now concentrated to provide advanced remote diagnostics, setup and monitoring features. In this domain, a new remotely controlled module is under design with the primary function to provide remote calibration of the acquisition cards by controlling an embedded current source and adjusting the analogue circuit of each channel to compensate component tolerance, noise and ageing.
The readout system for the upcoming Run3 upgrade of the LHCb experiment at CERN is based on a common readout board called PCIe40. This common FPGA-based board can be reconfigured to serve different subsystems within LHCb. A CI/CD pipeline was implemented in order to automatically cross-validate the tight interaction between our custom FPGA firmware and the associated DAQ and control software, all being actively developed in parallel. We present challenges and solutions for applying this kind of practices, traditionally limited mainly to the field of software engineering, also to hardware-in-the-loop validation of FPGA firmware and SCADA-based control systems.
The Ethernet network is a good control interface for distributed measurement systems.
The de facto standard in HEP experiments is IPbus. The experiences from using IPbus resulted in the proposal of a new Ethernet-based control interface optimized for quick parallel configuration of multiple systems.
The system ensures reliable delivery of control commands and responses.
The minimalistic local controller minimizes the negative effects of the Ethernet round-trip latency.
Usage of layer 2 Ethernet frames minimizes the FPGA resource consumption.
Implementation of the software part in Linux kernel space reduces dependency on specific software packages and libraries.
The Data Processing Boards (DPB) are the important component of the development version of the CBM readout system. Even though in the final version they will be replaced with the new Common Readout Interface (CRI) PCIe boards, they are still used for development and testing of new firmware features and for operation during the beam tests.
The paper describes the current state of the DPB firmware development. The special emphasis is put on the functionalities related to support the GBTX-connected front-end electronics.
For the ATLAS Phase-II upgrade, a complete new all-silicon inner tracker is planned, which will be readout at higher bandwidth due to finer granularity and higher occupancy.
While both subdetectors allow the usage of the GBT protocol on the downlink path, ITk Pixel needs a different uplink protocol due to the constrains given.
This work shows how a detector specific extension of the FELIX firmware could look like and which blocks are needed for the ITk Pixel subdetector. It also gives an outlook on how this can be beneficial for the ITk Strip subdetector as both subdetektors have common features.
A FPGA based time measurement electronics is developed for MRPC (multigap resistive plate chamber) detector in TOF (time of flight) applications. The basic structure is composed of an ultra-fast amplifier/discriminator (NINO) connected to MRPC and a dedicated FPGA based time-to-digital converter to measure TOT (Time-Over-Threshold), instead of charge. Preliminary tests show that the RMS of leading edge measurement of electronics is better than 15 ps, and that of TOT measurement by a single channel is better than 25 ps. By the cosmic-ray test with MRPC detector, the typical time resolutions is better than 50 ps, with an efficiency of 98%.
CMOS Pixel Sensors have been used in subatomic physics experiments for tracking devices. There are large quantities of hits generated by particles that coming from the detector beam background impacting tracking efficiency and reducing system bandwidth. We propose to design a CMOS pixel sensor with on-chip Artificial Neural Network (ANN) to tag and remove hits generated by background particles based on different features of these clusters. In this paper, we show and analyze the feasibility result of this idea by FPGA device implementation of an ANN.
At the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, the double-sided silicon strip sub-detector of the Belle II experiment is read out by 1748 APV25 chips.
FPGAs perform several calculations on the digitized signals. One of them is "Hit Time Finding": the determination of the time and amplitude of the signal peaks of each event in real time using pre-programmed neural networks.
This work analyses the precision and reliability of these calculations depending of various parameters, the respectively required FPGA resources and the software for offline-learning of the node parameters using synthetic and pre-recorded data samples.
The design and measurement results of two rad-hard, ultra-low power 10-bit SAR ADCs, fabricated in two CMOS 130 nm technologies, are presented. Both prototypes are fully functional achieving, in process A excellent linearity (INL, DNL < 0.3 LSB) and ENOB above 9.5 for sampling rate up to 50 MSps, and in process B a very good linearity (INL, DNL around 0.5 LSB) and ENOB around 9.2 with sampling rate up to 40 MSps. The power consumption at 40 MSps is, respectively, below 700 uW and 900 uW. The prototypes maintain their good performance for the doses up to 500 MRad.
For the high granularity end-cap calorimeter upgrade (HGCAL) of CMS, HGCROC-V1 was submitted in July 2017. It has 32 channels with the low noise preamplifier followed by 25 ns shapers, ADC and TDCs for the charge and time measurements. A 512 deep memory stores the digitized data until the readout is performed at 320 Mb/s. A trigger path, done by summing clusters of 4 adjacent channels, gives a compressed charge information at 40 MHz. Its data are serialized through a dedicated link at 1.28 Gb/s. The chip embeds all necessary ancillary services as bandgap circuit, PLL and reference voltage DACs.
In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called GEMROC2. Primary application of this ASIC is readout of 10×10 cm2 3-stage GEM detector, however, it can be used for readout of other types of Micro Pattern Gas Detectors.
The ASIC has been designed in 350 nm CMOS process. Its basic functionality and parameters have been evaluated using internal testability functions. System performance has been evaluated in tests of a fully equipped GEM detector module using X-rays. For argon based gas mixture we have achieved energy resolution below 18% FWHM for 5.9 keV line.
In order for the CMS electromagnetic and hadronic calorimeters in the barrel region (EB, HB) to support the high-luminosity upgrade of the LHC, the off-detector electronics (Back-End) must be replaced. For EB, the new Back-End has been designed to take over functions of the legacy Front-End electronics in order to handle the required increase in the sampling frequency and the granularity of the system. In addition, both upgraded EB and HB must cope with phase II upgrade technical requirements. On the roadmap to a prototype hardware platform, the Barrel Calorimeter Processor demonstrator board (BCP demo) has been designed.
The SAMPIC chip is based on the concept of Waveform Time to Digital Converter introduced in 2013. It permits performing timing measurements with a precision of a few ps directly on detector signals. The waveforms are digitized between 1.6 and 8.2 GS/s rate over 64 samples and Time Over Threshold measurement is integrated. A set of boards and DAQ system has been developed to record data with detectors in a real environment over 16 to 256 channels. The talk will focus on the new possibilities offered by the systems equipped with the latest chip version and report the performance measured.
A serial power scheme will be used for the new inner tracking detector for the Phase-II upgrade of the ATLAS experiment. New elements are required to operate and monitor a serially powered detector, including a detector control system (DCS), constant current sources and front-end electronics with shunt regulators.
A demonstrator for the outer barrel is built at CERN to verify the concept and operate multiple serial power chains. This includes all required elements from an interlock system to in-situ monitoring with the new DCS. In this talk we present how serial chains with up to 16 modules can be operated.
Hybrid pixel detectors are in overwhelming majority in today’s high energy physics experiments, but monolithic active pixel sensors (MAPS) in commercial CMOS technologies receive increasing interest due to their lower cost, easier detector assembly, and other advantages like lower material and higher granularity. Used for the first time in the STAR experiment, adopted for the ALICE experiment, they are being considered for the most aggressive applications, like the ATLAS HL-LHC upgrade, FCC and CLIC. This paper tries to give an overview of the improvements and challenges in sensor and front end design, architecture, speed, timing, radiation tolerance and system issues.
We report the design and irradiation results of a radiation-tolerant low-power 4x10 Gbps VCSEL Driver array IC in 65 nm CMOS. The driver IC consumes 130 mW at 4x10 Gbps and occupies 1.9 mm x 1.7 mm. The IC is capable of sustaining TID up to 300 Mrad and produces no errors after being irradiated with a total fluence of 2.8e15 20Mev neutrons over 36 hours. The IC is powered by 1.2 V for the core circuit and 2.5 V for the VCSELs. An on-chip power-on circuit is designed to ensure all transistors operate reliably during power-on and normal operation.
We present an optical transmitter (MTx+) and transceiver (MTRx+) based on LC-TOSA/ROSA. MTx+ and MTRx+ use the dual-channel VCSEL driver ASIC LOCld65, developed in a 65-nm CMOS technology and tested up to 14 Gbps. For the moment MTRx+ uses a GBTIA-embedded ROSA. The electrical connector is the same as that in SFP+. Both MTx+ and MTRx+ receive multimode LC-connectorized fibers. The module is below 6 mm in height and can be panel or board mounted. Prototype modules and measurement results are presented.
Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML for boosted-jet tagging with deep networks at the LHC. We map out resource usage and latency versus network architectures, to identify the typical problem complexity that HLS4ML could deal with. We discuss possible applications in current and future HEP experiments.
The Muon-to-Central Trigger Processor Interface(MUCTPI) of the Level-1 muon trigger of the ATLAS experiment is being replaced for the LHC Run-3. The upgraded MUCTPI is implemented as an ATCA module using high-end FPGAs and high-density ribbon fibre-optic modules to integrate over 270 multi-gigabit optical inputs and outputs on a single board.
The MUCTPI also features a System-on-Chip(SoC) with an ARM processor running an embedded Linux OS to control the module. We present results from the hardware and firmware validation of the second prototype based on Xilinx/Ultrascale+ FPGAs, and about the SoC used to interface to the experiment run control system.
The Silicon-Strip readout ASIC (SSA) for the pixel-strip module of the Phase II upgrades of the CMS Outer Tracker detector has been prototyped in a 65nm CMOS technology employing radiation tolerant design techniques. The SSA provides real-time primitives for the on-detector particle momentum discrimination and for the readout of the complete triggered events. This contribution will present the test results and the performance evaluation data from the first SSA prototype as well as radiation tolerance characterization results.
The design and measurement results of a prototype readout ASIC for the luminosity calorimeter at future linear collider are presented. The proof-of-concept ASIC, comprising 8 channels with a variable gain front-end, a differential shaper and a 10-bit SAR ADC in each channel, was fabricated in CMOS 130~nm technology. The prototype is fully functional, achieving good linearity in a wide input charge range with a SNR for MIP signals of about 25 in the high gain mode. The ASIC consumes about 1.5~mW/channel. The design of a full, 32-channel SoC type FLAME, currently under development, will also be covered in this contribution.
This work presents a novel method for solving the negative effects of charge sharing phenomenon. In contrary to the existing solutions, where the hit position is determined through additional analog signal processing, the presented approach is based on a digital algorithm, called COGITO, which finds the center of gravity of a group of pixels that received and processed fractional charges resulting from a charge shared event. The algorithm concept and its implementation details are presented, followed by measurements results obtained with a test chip designed in a 55 nm CMOS process.
The main goals of the ATLAS New Small Wheel (NSW) upgrade are to reduce fake triggers from backgrounds hits and improve the tracking efficiency in the high rate environment at the LHC. A low-latency hardware trigger processor is being developed for the NSW in the muon spectrometer. The processor will fit candidate muon segments in the small-strip Thin Gap (sTGC) and MicroMegas (MM) chambers in real time, improving significantly the background rejection. We present the overall electronics design and implementation of two pure-FPGA algorithms in an ATCA architecture for finding track segments using trigger data from the sTGC and MM.
For LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET.
An upgraded L1 Topological Processor will allow to select interesting physics events applying topological constraints.
To achieve up to ~3 Tb/s input bandwidth and substantial processing power with tight latency budget of <390 ns, the trigger boards host up to four Ultrascale+ FPGAs. Design and test results of full-scale prototypes from integrated tests will be reported.
Serenity is an ATCA prototyping platform designed to explore alternative, novel design choices for CMS Phase-2. It uses a newly available interconnect technology from Samtec (z-ray) to mount a removable processing unit (FPGA) that should mitigate risk and provides significant flexibility in processing unit choice and connectivity. The presentation will explore the pros and cons of using an industry standard Computer-On-Module, running x86 Centos and a small service FPGA for low level control. Specially designed Kapton heaters will be used to validate the thermal design, while structural test results will be presented for the heatsink design.
Unlike today when “digital turns into analog” and “analog turns into digital”, back in the late 1990s, the separation between analog and digital was unmistakable and vast. The design techniques, automation flow (or the lack of it), or even the way of designers' thinking were simply incompatible. Probably the only major area that was blurring these boundaries was a read channel for magnetic recording in hard disk drives. It employed precise continuous-time filtering combined with ultra-high speed discrete time analog signal processing plus sophisticated digital processing. Having been fully immersed in that way of thinking and then moving to an RF group within Texas Instruments has produced an eye-opening experience. The read channel was sampling at 750MS/s and GSM then was only 900MHz so the CMOS technology was becoming fast enough. Why not exploit the digital and sampling techniques to directly digitize the RF signal? Of course, doing so blindly would burn too much power to make it practical but why not exploit another idea of magnetic recording: time-domain information? The information has traditionally been encoded as voltage (or sometimes current), but why not use time? This immediately led to the idea of time-to-digital converters (TDC) to solve the pesky problem of phase error filtering in PLLs. When a digitally controlled oscillator (DCO) was added to it, the resulting ADPLL is just the history.
Special Evening Talk by Prof. W. Sansen with the title 'Analog design and me'
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme requirements, such as: 50x50 µm pixels, high rate (3 GHz/cm$^2$), unprecedented radiation levels (1 Grad), high readout speed, serial powering. As a consequence a new readout chip is required.
In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator designed in 65 nm CMOS technology, integrating a matrix of 400x192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with comprehensive test results on single chips and modules.
A major upgrade for the ATLAS Inner Tracker at the Large Hadron Collider (LHC) is scheduled in 2026. The depleted CMOS pixel sensors on high resistivity substrates in LFoundry 150 nm technology have been proven to be promising for this upgrade. Recently two large demonstrators, one based on hybrid concept called LF-CPIX and the other based on monolithic concept called LF-MONOPIX have been produced. The chips were fully characterized in the lab and irradiated up to 150 Mrad under the 24 GeV Proton Synchrotron at CERN. In this work we will describe the behaviour under radiation of the two prototypes.
In this contribution, we will present the status of the electronics system of the triple-GEM detectors for the CMS GE1/1 upgrade, which is planned for installation in 2019-2020, as well as the performance of ten prototype detectors which have been installed in CMS since 2017.
For this new CMS muon sub-detector, a new front-end chip, the VFAT3, has been designed. The VFAT3 communicates with the back-end microTCA electronics through the GBTx chipset and the versatile link. Each of the 144 triple-GEM detectors has 24 VFAT3s, 3 GBTx chipsets, and a Virtex-6 FPGA, all powered by 10 FEAST DC-DC converters.
The present ATLAS small wheel muon detector will be replaced with a New Small Wheel detector in 2019. The frontend electronics will be implemented in about 8000 boards including the design of 4 custom ASICs capable of driving trigger and tracking primitives to the backend trigger processor and readout system. The large number of readout channels, short time available to prepare and transmit trigger data, large volume of output data, harsh radiation environment, and the need of low power consumption all impose great challenges on the system design. We will present the design and status of the whole system.
The central building block of the Upgrade are staves and petals which host up to 14 modules per side. The incoming data is sent to the EoS and multiplexed by the lpGBT chips on 10 Gbit/s links and sent via optical transmitters (VL+) off-detector. Prototype boards have been designed, manufactured and used with the present chip versions of the GBTX /GBT-SCA chip family. This talk will summarize the experiences with the EoS prototype sitting at a single-point-of failure location. An outlook for an EoS with the faster and less power-consuming lpGBT chips and its integration will be provided.
Cochlear implants are the first device to successfully restore neural function. They have instigated a popular but controversial revolution in the treatment of deafness, and they serve as a model for research in neuroscience and biomedical engineering. After a visual tour of the physiology of natural hearing the function of cochlear implants will be described in the context of electrical engineering, psychophysics, clinical evaluation, and my own personal experience. The audience will have the opportunity to experience speech and music heard through a cochlear implant. The social implications of cochlear implantation and the future outlook for auditory prostheses will also be discussed.
About the speaker:
Ian Shipsey is a particle physicist, and a Professor of Physics at Oxford University. He has been profoundly deaf since 1989. In 2002 he heard the voice of his daughter for the first time, and his wife's voice for the first time in thirteen years thanks to a cochlear implant.
The H35DEMO is a HV/HR-DMAPS large area chip fabricated in AMS 350nm HV-CMOS technology. It includes two monolithic matrices with pixels of $50\times250\mu m^2$ with analog electronics embedded in a Deep N-WELL also acting as collecting electrode.
Chips were irradiated with both protons and neutrons up to the radiation doses expected for the outermost layers of the ATLAS pixel detector at HL-LHC and their radiation hardness was investigated in beam test experiments.
Results of these characterisations will be presented and a new LFoundry 150nm production including HR/HV-MAPS featuring sensors with $50\times50\mu m^2$ pixels will be introduced.
The nSYNC is a radiation tolerant custom ASIC, developed in UMC 130 nm technology for the readout electronics upgrade of the LHCb Muon System. The chip will be exposed, over ten years of operation, to a total dose of 130 Gy and fluence of 2 · 1012 cm−2 1MeV neutrons equivalent. We present the results of radiation tests performed at the Catana facility (INFN, LNS) with 60 MeV protons beam, up to 1200 Gy, and at Cagliari X-Ray facility, with a particular focus on logic functionalities, TDC performance, measurements of Single Event effects and Total Ionizig Dose effects.
The CMS detector for LHC Phase-2 will be read out at 750 kHz for an event size of 7.5 MB. The optical links from detector front-ends are aggregated in ATCA back-end boards. A DAQ-and-Timing Hub (DTH) aggregates data streams from back-end boards over point-to-point links, provides buffering and transmission over 100Gb/s TCP/IP Ethernet links. The DTH is also responsible for distributing timing, control and trigger signals to the back-ends. This paper presents the requirements and the design of the DTH and the first prototype foreseen for Q4-2018. Results with Ultrascale development kits and serial HMC memories will be presented.
The readout system for triggerless High Energy Physics experiments, recently under intense development, contain an aggregation and data processing modules. They are responsible for collecting data from multiple input links, pre-processing and packaging them into containers for the event selection module located next in the readout chain.
The presented article discusses design considerations for such module, inspired by requirements of the readout in the CBM experiment and prepared for the DPB/CRI aggregation module.
For developing a new generation of Resistive Plate Chamber detectors, we present here an improved tapped-delay-line Time-to-Digital Converter (TDC) for time-over-threshold (TOT) measurement, which has been implemented on a low-end, 28nm cyclone V-GT FPGA. Our proposed approaches include signal reshaping and optimized routing, as well as edge-detecting and encoding only a small segment of signal around edge. The latter saves at least 50% of the FPGA’s hardware resource (for each channel). Preliminary tests on the FPGA have shown 12-ps time resolution for leading and trailing edges and 20-ps resolution for TOT measurements with 2-ns pulse duration, and 5-ns dead time.
Coordinating firmware development among many international collaborators is becoming a very widespread problem in particle physics. Guaranteeing firmware synthesis with P&R reproducibility and assuring traceability of binary files is paramount. Our HDL managing tool tackles these issues by exploiting advanced Git features and being deeply integrated with HDL IDE, with particular attention to Intellectual Properties handling. In LHC Run3, the ATLAS L1Calo Trigger system will be upgraded with new feature extraction and readout modules. Our tool, handling firmware development for these modules, was developed in Python and integrated with CERN Gitlab (using Web-Hooks, Gitlab API) and Xilinx Vivado.
Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as report on results of the ongoing development program.
One of the challenges facing the system-level design of the ATLAS ITk Strip Detector is the understanding of the TID induced leakage current in the chosen 130nm CMOS technology. The effect of ionizing radiation on the current increase of the ABC130 readout ASIC has been studied at various different dose rates and temperatures using x-ray tubes and Co-60 sources. In addition, the efficacy of pre-irradiation of chips and the variation across wafers and batches has been studied. The results shown here allow a better understanding of the effect of TID on final detector systems and associated system design.
The LHC planned two phases of upgrades to improve the instantaneous luminosity. An accompanying upgrade of the readout electronics for the ATLAS detectors is planned to handle the increased trigger rates and readout data bandwidth. Due to high flexibility and short development-cycle, FPGA-based systems are increasingly popular within the high-energy physics community. We present here a multi-layer SEU mitigation scheme to strengthen the system against the harsh radiation environment experienced by the electronics within ATLAS. The scheme is quite general, and therefore may benefit experiments and applications beyond ATLAS and high-energy physics. Both design and experimental results will be discussed.
Considered as a back-up solution of the upgraded LHCb RICH sub-detectors, the antifuse FPGAs have been seen as a viable solution to be used in the harsh radiation environment of high energy physics and space experiments. This study is a summary of test beam results performed on a 0.15 µm CMOS antifuse device with a proton beam. We are characterizing the FPGA behavior under large TID and high dose rate conditions, and we are using the obtained results to extrapolate to HL-LHC conditions.
The read noise of CMOS image sensors has been reduced by a factor 10 in the last 15 years. As a result, photon-counting applications are now in reach with CMOS image sensor technology. The talk will address the most important measures that have led to this noise reduction, such as CMOS scaling, improved readout circuits and low-noise CMOS transistor process technology. In most cases, the low-noise image sensors use a rolling shutter to control the exposure. Today, we also see a large interest in global shutter image sensors for a variety of consumer, automotive and industrial applications. In global shutter image sensors, all pixels acquire the image at the same time. The more complex global shutter pixel structure poses some challenges for noise reduction techniques which will also be addressed.
The CMS Barrel Muon Track finder is a component of the Level-1 Trigger which performs track reconstruction and momentum measurement in the central region of the CMS experiment.
The current algorithm uses precalculated look-up tables to estimate the track parameters. A new approach will be presented deploying a Kalman filter algorithm that
exploits DSP resources in modern FPGAs, is prototyped in C using High Level Synthesis tools, and is implemented and tested in the current running CMS trigger.
A versatile ATCA platform featuring Ultrascale+ FPGAs and high speed fly-over optics proposed to host this algorithm in HL-LHC will be discussed.
This paper presents the results of a Single Event Upset (SEU) test with heavy ions on a shift register manufactured in a 28nm commercial CMOS technology, interesting for future upgrades for HL-LHC. Results will show the cross section curve in a Linear Energy Transfer (LET) range between 3-60 MeV∙cm^2/mg for different patterns.
A fast continuously sampling digitiser have been designed for acquiring the signal from LaBr3 scintillating crystals detectors. They are foreseen in the FAMU experiment, aimed at spectroscopic measurements of muonic hydrogen, possibly providing insights into proton radius puzzle. The board, named GSPS, is an FMC mezzanine which hosts two off-the-shelf sampling ADC used in interleaved timing architecture, achieving 1 GS/s rate. Interleaved technique allows us to keep both lower production costs and simple acquisition system avoiding complex interface protocols like JESD204. The board will be described, tests and achieved performances will be shown and discussed.
Current existing alpha/beta counters use gas-flow detectors becasue of their low energy detection threshold compared to Passivated, Implanted, Planar Silicon (PIPS®) detectors. However, gas based systems suffer drawbacks with respect to safety and required infrastructure for the gas. The latest evolutions of the characteristics of PIPS® detectors allow to reach a lower energy threshold, that is comparable to gas-flow detectors. For these new alpha/beta counting systems, redesign of the front-end electronics is necessary. In this work we focus on the design of a bipolar shaping amplifier with adjustable gain and present the calculations, simulations and validation.
Time response of a Silicon Photomultiplier (SiPM) depends on some of the intrinsic parameters of the sensor. Combining multiple small SiPM instead of one with larger area will reduce detector capacitance at electronic level, which can be translated into a lower jitter, and thus better Coincidence Time Resolution (CTR) of a PET system. This work provides a framework by combining GATE and an electrical simulator. This will enable a global optimization of the PET system including the scintillator, the sensor (sensor size, pixel pitch, dead area and capacitance) and the readout electronics (input impedance, noise, bandwidth and summation).
Radiation-hard, compact, low-mass, hybrid GaN and CMOS integrated module DC-DC converter has been designed. The converter has an input voltage of up to 18V regulated down to an output voltage of 1.5V, with 7A maximum load current. It exhibits >70% efficiency. Discrete GaN transistors are used for the power stage, and the controller circuitry and power device drivers are integrated on a 0.35um CMOS chip. RHBD techniques have been implemented to meet TID levels ≥150 megarad(Si). This presentation discusses the successful test results of the custom-designed CMOS driver/controller ASIC and the whole converter module that uses this ASIC.
We present a new kind of silicon device: a High-Voltage vertical JFET, conceived as a candidate for the High-Voltage Multiplexing switch in the ATLAS upgrade of the silicon microstrip Inner Tracker (ITk). Both n-type and p-type HV-JFETs have been successfully fabricated in the silicon processing facility of Brookhaven National Lab. Probe station measurements of un-irradiated devices show low leakage current and high breakdown voltage (up to 600V) in the OFF state, and high currents in the ON state. We’ll present for the first time the design, the technology process flow, and the electrical characterization of these devices.
The CMS Outer Tracker planned for the HL-LHC Upgrade contains strip-strip and pixel-strip silicon modules. Each of them includes two high-density front-end hybrid circuits, equipped with flip-chip ASICs, passives, connectors and mechanical structures. Several strip-strip hybrid prototypes have been produced using the CBC2 front-end ASIC. Feedback from these developments helped improving the hybrid’s testability and the production yield. The availability of the concentrator ASIC’s footprint and of the new CBC3 front-end ASIC enables the design of all strip-strip hybrid variants. In this work the development milestones and the final designs are presented together with chosen solutions.
This work presents an automated solution for testing medium scale ASIC productions. Small scale prototype ASIC production are tested by hand in order to validate ASIC designs, and big scale ASIC productions are validated using industrial methods either checking directly the wafer or using specific instrumentation. Scientific experiments usually require producing thousands of ASICs that do not fall in any of these categories. In order to solve this problem, we have developed a testing rig to automate this procedure. Medium scale ASIC productions can be tested without having to do so manually and avoiding the cost of industrial testing solutions.
The Mu2e electromagnetic calorimeter is composed of un-doped CsI crystals coupled to large area Silicon Photomultipliers (SiPMs). A custom SiPM layout consisting of 2 series of 3 6x6 mm^2 UV-extended monolithic SiPMs has been developed. So far, the production of 4000 pieces is ongoing and a detailed Quality Assurance (QA) process is being carried out on each monolithic SiPMs with an automatized test station that allows to test up to 20 photosensors together. We present the design of the test station and the measurement techniques, as well as a summary of the results obtained from the first tested batches.
The Ring Imaging Cherenkov detectors are key components for particle identification in LHCb experiment at CERN. The present RICH photodetectors will be replaced by multi‐anode photomultiplier tubes and front‐end electronics capable of operating at a 40MHz input rate. About 33.000 CLARO8 packaged ASICs have been manufactured and tested on a dedicated automatic pick‐and‐place station. About 4200 Front‐End (FEB) and 1300 Back (BkB) boards hosting and connecting the ASICs are being checked with test setups which are going to be used also to characterize the fully assembled Photon Detector Modules. This presentation describes the dedicated test systems, procedures and results.
The ATLAS Experiment will upgrade its Inner Tracking system for the High-Luminosity-LHC with an all-silicon system. The strip part will be based on individual modules, constructed by gluing the front-end hybrids directly onto the strip side of the sensors. The modules will then be glued onto a low-mass local support core with services integrated. We have constructed the first double-sided module made from full-size sensors by gluing modules on a reduced-size core. We will report on the experience gained and discuss results obtained from running this module, with emphasis on signal integrity and noise performance.
The ATLAS Experiment will upgrade its tracker with an all-silicon Inner Tracker (ITk) for the HL-LHC, comprising pixel and strip detectors. The strip detector is based on silicon strip sensors, which are read out by low mass radiation-hard circuits carrying custom designed radiation-hard ASICs in 130 nm technology. The circuits are made from flexible PCB multi-layer copper polyimide constructions. The ASICs are glued onto the flex and connections are made by wire-bonding. This contribution discusses the evolution and electrical performance of various hybrid prototypes necessary to equip the forward region of the detector, as well as their final development.
Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple Modular Redundancy (TMR) with clock skew insertion, a system level redundancy technique is a common practice by designers to mitigate soft error rates. However, the optimal spacing between memory elements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASIC development under the framework of the CERN RD53 collaboration to characterize the soft error rates against the separation spacing and clock skew between memory elements in a TMR. This article describes the architecture and design aspects of the RD53SEU test chip.
The ATLAS experiment at the LHC is undergoing a major upgrade to handle the higher collision rate that will be provided by the High-Luminosity LHC. A major component of the ATLAS Phase-II upgrade is the Inner Tracker, an all-silicon detector featuring novel n+-in-p microstrip sensors. Miniature sensors implementing this design are tested for their radiation tolerance at the upgraded characterisation facility of the University of Sheffield. After the sensors irradiation, charge collection efficiency and cluster size measurements, taken with the ALiBaVa system utilising β-radiation, quantify their operational robustness. A review of the facility upgrade along with preliminary results is presented.
This paper proposes a 1 GHz Delay Locked Loop (DLL) which was processed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. It has a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter (TDC), and achieves an rms jitter below 800 fs. One of the improvements to this low jitter comes from the bang-bang phase detector (PD), which is designed to have a very small hysteresis of only 480 fs.
We have developed an updated DaughterBoard design for control and readout of the upgraded ATLAS hadronic Tile Calorimeter electronics for HL-LHC. The new design migrated from two QSFPs to four SFP+ modules handling: 4×9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and 2×4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT samples, while the downlink receives control, configuration and LHC timing. TMR, FEC and CRC strategies, plus a double redundant design with radiation tolerant components, minimize single failure points and improves resistance to single-event upsets caused by minimum ionizing and hadronic radiation.
During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out the front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). This work will present the irradiation campaigns performed on the V2, V3 and V4 prototypes of the SAMPA chip. The irradiation campaigns have been performed using the Heavy-Ion facility at UCL (Université Catholique de Louvain - Belgique) and the Single-Photon laser facility at IES (Institute of Electronics and Systems - Montpellier).
The readout board for the ALICE TOF detector named DRM2 is now in the production phase: 88 boards are being produced (72 are needed in the experiment). Since the board will operate in a radiation environment (0.13 krad total dose expected in 10 years), a complete irradiation campaign at the component level was performed. We will focus on the Microsemi Igloo2 FPGA and two Avago optical transceivers radiation tests with a 100 MeV proton beam, available at the facility operated by INFN-TIFPA at the Centro di Protonterapia in Trento. This paper will also focus on the production test strategy.
Vacuum in the ARCs of the LHC is crucial to minimize beam – gas interactions and to assure thermal insulation of cryostats and helium distribution lines. Several hundred of sensors with their associated conditioning electronics are installed across the ARCs for both beam and insulation vacuum measurements. Simulations predict that radiation levels will greatly increase during HL-LHC era. Therefore, new radiation tolerant conditioning electronics for vacuum measurements are required to withstand such conditions. This paper describes the design of these new electronics, their qualification tests and implementation within the vacuum controls architecture foreseen during the long shutdowns of the LHC.
The WaveCatcher systems are a family of powerful and low cost digitizers. Their number of channels ranges between 2 and 64. They easily replace oscilloscopes in numerous applications. They are based on the SAMLONG ASIC which samples the signal between 400 MS/s and 3.2 GS/s over 12 bits with a bandwidth of 500 MHz.
The systems can also be used as TDCs for high precision time measurement. Sampling time precision after calibration is indeed better than 5 ps rms at 3.2GS/s. They house USB and secured Gbit-UDP interfaces. A powerful software and a complete C library are also available.
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The read-out of the ITk pixel system will be most challenging in terms of data rate. First test of read-out concepts are performed with the ITk Pixel “demonstrator”, a system composed of several ITk-style modules with in total 120 FE-I4 read-out chips. Their read-out is realised with data aggregation via GBTx chips transmitting data optically to “Cluster On Board” (COB) ATCA-boards acting as off-detector components. The system layout and first test results will be presented.
Linear array detectors with high spatial resolution and MHz frame-rates are essential for high-rate experiments at accelerator facilities. We have developed KALYPSO, a line array detector with 1024 pixels operating at 10 Mfps. To improve the spatial resolution and sensitivity at different wavelengths, novel Si microstrip sensors have been developed with a pitch of 25 µm. Furthermore, to enable measurements of the beam profile with a repetition time of 2 ns, a sensor based on Low Gain Avalanche Detector (LGAD) coupled with a SiGe readout is under development. The detector system and the characterization of the sensors will be presented.
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate. Simulation of the on-detector electronics based on a trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission is implemented electrically, realised by “active cables” integrating data aggregator and equalizer ASICs. The system layout and updates on simulation and test results will be presented.
The CMS Drift Tubes (DT) readout system has been upgraded during the 2017-2018 technical stop to a new uTCA-based system (uROS) to deliver the performance required by the increase of LHC luminosity. It comprises 3 uTCA crates with up to 25 boards, each processing 3 sectors from each CMS wheel. The uROS board is built around a Virtex-7 FPGA, and is able to receive 72 input links. The 240-Mbps inputs are deserialized using oversampling and adaptative phase detection. Event building, synchronization, data integrity monitoring and error correction have been implemented. The uROS system is fully operational, taking collision data satisfactorily.
CMS ECAL Phase2 Front-End(FE) card is designed to provide streaming of the data generated on the Very-Frond-End(VFE) cards to the back-end electronics. FE card will use the components developed within the VersatileLink project. It will contain four or six lpGBT ASICS with corresponding VersatileLink+ optical modules. Prototype FE card was developed to validate the clock distribution, high speed data links and other technical features of the future design using the currently available GBT and VersatileLink components.
The current version of the upgrade FE card design will be discussed as well as the design and test results of the GBT-based prototype.
We present the Detector Control System (DCS) system being designed for triple-GEM detectors to be installed in 2019-2020 in the CMS muon endcaps for HL-LHC. Beginning of 2017, 10 triple-GEMs, called slice-test, have been installed for the very first time in CMS. Therefore the GEM DCS had basically to be designed from scratch. We will describe its key features (hardware and software), the main developments and the important commissioning steps which were required to allow its integration within the central CMS DCS to enable the data acquisition of the slice-test GEM data by the central DAQ system of CMS.
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground Neutrino experiment with a 20-thousand-ton liquid scintillator detector at 700-meter deep underground. All the signals coming from the almost 18000 Central Detector 20-inch photomultipliers (PMTs), will be digitized thanks to high-speed high-resolution waveform full sampling technique. An Analog to Digital converter Unit (ADU) which will be located very close to the PMTs, inside an underwater box, has been designed to digitize the input signal. This paper introduces the details of the ADU design, then describes the ADU test system and the first ADU test results.
Jiangmen Underground Neutrino observatory (JUNO) is a neutrino medium baseline experiment in construction in China, with the main goal to determine the neutrino mass hierarchy. A large liquid scintillator (LS) volume will detect the antineutrinos issued from nuclear reactors. The LS detector is instrumented by around 20000 large photomultiplier tubes. The JUNO electronics readout system consists of two parts: (i) the underwater front-end electronics system and after 100-meters-long Ethernet cables, (ii) the back-end electronics system. Back end card is used to link the underwater box to the trigger system.
We will present the design of the BEC and test results.
Considerable enhancements are foreseen for the Drift Tubes (DT) subdetector during Phase-2 CMS upgrade. The new HL-LHC CMS Trigger/DAQ requirements exceed the present capabilities of the on detector electronics (MiniCrate). Therefore, as a consequence of the higher L1A rate set by CMS, as well as MiniCrate maintainability and chamber aging mitigation arguments, all MiniCrates will be replaced during LS3. The phase-2 on detector electronics for DT will consist of only a single type of board called OBDT (On Board electronics for Drift Tubes). A description of it will be given along with the status of the prototype and validation tests.
The High-Granularity Timing Detector (HGTD) will improve the performance of the ATLAS detector for the Phase II upgrade of the HL-LHC by providing precise timing information. The detector base unit consists of a hybrid module of a 2x4 cm$^2$ Low Gain Avalanche Detector (LGAD) bump-bonded to two ASICs and wire-bonded to a Flexible Printed Circuit (FLEX cable). The latter transmits high-speed signals (1.28 Gbps) for data readout while providing power and HV to the module. Its design must fulfil the HGTD requirements both mechanically and electrically, combining different signal types. Test results of our initial prototype are presented.
The Level-1 Data Driver Card (L1DDC) was designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. L1DDC is a high speed aggregator board capable of communicating with multiple front-end electronic boards. It collects the Level-1 data along with monitoring data and transmits them to a network interface through bidirectional and/or unidirectional fiber links at 4.8 Gbps each and distributes trigger, time and configuration data coming from the network interface to the front-end boards.
In this paper, the L1DDC boards will be described and the results from radiation tests will be presented.
In order to save the space in the underground counting rooms during the ATLAS phase II upgrades, a project dedicated to the study of the impact of taller rack integration in the actual counting rooms was launched analyzing its cooling performance and the impact on the cooling infrastructures.
A new 63U prototype rack equipped with three ATCA shelves with open bottom to top airflow, high power dissipating load blades, three new prototype 2U heat exchangers and various sensors was installed in a lab. Impact of stocking three ATCA crates on the cooling performance was checked alongside with other critical aspects.
The CMS ECAL barrel electronics will be upgraded for the HL-LHC to comply with increased latency and bandwidth requirements of the Level 1 trigger, to preserve detector performance despite the increased instantaneous luminosity, and to provide a precision timing measurement in addition to energy. The chosen solution includes a custom dual gain trans-impedance amplifier implemented in a 130nm CMOS process and a dual ADC ASIC implementing gain selection and data compression implemented in a 65nm CMOS process. Test results and the development plan for the CMS ECAL barrel front end electronics system up to installation readiness will be presented.
The Embedded Local Monitor Board (ELMB) is a microcontroller based plug-in module with CANopen communication protocol. It has been widely used in LHC systems and experiments for slow-control and monitoring purposes, providing multiple galvanically isolated analog and digital inputs and outputs.
While these modules have shown excellent performance in the past 15 years, a replacement is necessary due to the obsolescence of spare components and much higher radiation tolerance requirements within the coming HL-LHC upgrade.
Three development paths are proposed. One fully backward compatible and two others with different concepts but with higher radiation tolerances.
The second generation of the 8 channel PaDiWa-AMPS front-end board was recently assembled at the GSI department for Experiment Electronics (GSI EE). The board implements precise TDC and QDC measurements optimized to read out the 978 PMTs of the HADES electromagnetic calorimeter (ECAL). The HADES ECAL detector is currently under commissioning. In this contribution the read-out scheme of the ECAL and first results of a production beam time with the HADES will be presented.
Work supported by the DFG through GRK 2128 and VH-NG-823.
The CMS High Level Trigger has been designed to run a streamlined version of the offline reconstruction software on a traditional computer farm. To address the challenge presented by the Higher Luminosity-LHC, CMS is evaluating a heterogeneous computing platform for the HLT, aiming to deploy a prototype in production already during Run 3. The R&D work on the software framework and reconstruction algorithms began in 2017, aiming to produce a “demonstrator” working in realistic conditions by the end of 2018. This presentation will describe the results of the development and the characteristics of the system, along with its future perspectives.
The Fast Tracker(FTK) is an integral part of trigger upgrade program for
the ATLAS experiment. At LHC Run2, which started operation in June 2015
at a center-of-mass energy of 13 TeV, the peak luminosity has exceeded $2×10^{34}
cm^{−2}s^{−1}$ and the LHC produce an average of 60 simultaneous collisions.
The higher luminosity demands a more sophisticated trigger system with
increased use of tracking information. The Fast Tracker is a highly-parallel
hardware system that rapidly reconstructs tracks in the ATLAS inner detector
at the triggering stage. This paper focuses on the Input Mezzanine Board that
is an input module of entire system.
A trigger processor demonstrator card has been designed for the CMS Barrel Muon Trigger (BMT) upgrade at HL-LHC. A two-layer system design is foreseen for BMT. Layer-1 hosts the trigger primitive algorithms and preliminary tracking algorithms. Layer-2 hosts the main track finding algorithm, the correlation between the tracks from the muon system and the track-trigger for best possible estimate of the muon momentum. The processor card is a demonstrator for Layer-1 and is instrumented with a Kintex UltraScale FPGA and optical links at 16 Gbps. The Hardware and Firmware design as well as information of the performance is presented here.
Real-time track reconstruction in high energy physics experiments at colliders running at high luminosity is very challenging for trigger systems. To perform pattern-recognition and track fitting, artificial Retina or Hough transformation algorithms have been introduced in the field which have usually to be implemented in the state of the art FPGA devices. In this paper we report on simulated performance of Retina in a detector configuration made of concentric detection layers with high magnetic field as well as on performance of several possible firmware implementations on a Kintex-7 FPGA.
To face the harsh environmental conditions in high energy physics, the systems have to find the right balance between high availability and fault tolerance. In response to the new failures during the runs, the graceful degradation has to be adaptive, with the minimum of impact on the data acquisition chain. To improve the Trigger Concentrator Cards, during the CMS Level-1 trigger upgrade, the approach of an hardware/software co-design has been used to benefit from the performances and flexibility of these respective areas.
Single muon triggers are crucial for the physics programmes at hadron collider experiments. To keep the trigger rates reasonable low they must be highly selective.
Muon system at LHC experiments and at future colliders use two muon chamber system for triggering. Fast trigger chambers, identifying the bunch crossing and providing a course momentum estimation, and slower precision chambers, for precise measurements of the muon trajectory.
A fast lightweight track finding algorithm, based on the Hough Transform and Linear Regression techniques, has been designed and implemented on a Zynq SoC device, reconstructing successfully muon tracks in a single trigger sector.
We propose a novel fast track finding system capable of reconstructing four dimensional particle trajectories in real time using precise space and time information of the hits. The fast track finding device that we are proposing is based on a massively parallel algorithm to be implemented in commercial field-programmable gate array using a pipelined architecture. We will present studies of expected tracking performance and first results based on a hardware prototype.
The CMS experiment implements a sophisticated two-level triggering system composed of hardware-based Level-1, and a software-based High Level Trigger. A new Level-1 trigger architecture improves the performance at high luminosity experienced during Run II. The upgraded muon trigger combines information from the three muon detectors - Cathode Strip Chambers (CSC), Drift Tubes (DT) and Resistive Plate Chambers (RPC) - to obtain a better efficiency and lower rates. The algorithms, designed both for precision measurements and searches of new physics, and the performance of the upgraded muon trigger system based on proton-proton collision data collected in Run II will be presented.
Currently, various hardware concepts and technologies are being evaluated for the CMS Phase 2 Tracker off-detector processing system. The back-end electronics system comprises the Data Trigger and Control (DTC) system, the Track Finding Processors (TFP) and the DAQ \& TTC Hub (DTH). We designed UltraFlex as an ATCA based technology demonstrator with two main purposes: to implement a flexible approach to evaluate different optical high-speed transceivers and to provide a novel centralized slow control and board management solution based on Zynq Ultrascale+ (US+) System-on-Chip (SoC).
The upgrade of the ATLAS tracking detector for the HL-LHC requires radiation hard silicon sensor technologies. For the development of depleted CMOS sensor for ATLAS we combined small electrodes with minimal capacitance and advanced processing to achieve radiation hard CMOS for the ITK. We developed and tested a first full-size depleted CMOS sensor based on a 180nm imaging process. The ''MALTA'' sensor combines special low-noise/low power front-end using small electrodes with a novel high-speed/asynchronous readout architecture for high hit-rates. The presentation will summarize design and initial measurements on analog and digital performance as obtained in lab and beam tests.
We report the design, implementation, and measurement results of a 2.56 GHz PLL (COLDATA PLL) and a 1.28 Gbps 10:1 serializer (COLDATA SER) IC in a 65 nm CMOS process as part of the COLDATA prototype IC for the Deep Underground Neutrino Experiment (DUNE). The PLL employs a trip-path architecture with a temperature compensated path to achieve small VCO frequency drift, stable bandwidth and low jitter across a wide temperature range. The measurement results demonstrated that the PLL and SER IC can operate and achieve the targeting performance at both room temperature (300K) and cryogenic temperature (77K).
To maintain high trigger efficiencies and stable rates during significant changes to beam conditions throughout 2017, the CMS Level-1 calorimeter trigger required dynamic and flexible operation. Successfully running since 2015, utilising Xilinx Virtex 7 690 FPGAs and 10 Gbps optical links, the versatile design has enabled quick adaption to improve algorithms to mitigate large rates from high pileup and changes in detector response, and as the LHC responded to a number of unexpected challenges. Operational experience and lessons learned will be presented, and how they will inform important decisions in the design and implementation of the Phase 2 trigger upgrade.
Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, performances of the final prototypes and results of the system integration tests will presented along with the overall system design.
The silicon modules of the Phase-2 CMS Outer Tracker feature service hybrids, which are flex PCBs that will carry radiation-tolerant DC-DC converters, the Low Power GBT chip, and a VTRx+ module. The strip modules are powered via a two-step DC-DC conversion scheme, while the data from the front-end hybrids are collected and serialized by the LpGBT, and passed on to the VTRx, which performs opto-electrical conversion. A prototype of this board, featuring FEAST2, the GBTx, the VTRx (all by CERN), and a commercial DC-DC converter, was developed, and we will present the experience from characterization and testing of this board.
Extreme miniaturization of packages and high-density interconnects are routinely demanded by many HEP applications. The following challenges are key to satisfy these demands:
- How to build smallest (volume, foot-print and weight) systems (Miniaturization)
- How to decrease the die spacing in-between individual sensor (Placement accuracy)
- How to integrate optical data transmission systems (Miniaturization/Placement accuracy)
- How to better dissipate heat (Thermal management)
- How to mix technologies (Hybrid)
This overview covers many aspects of packaging technologies suitable for such constraints, such as:
- Taiko wafer thinning
- bumped wafer thinning technologies
- wafer bumping with or without redistribution layers (RDL)
- Fan-out technologies
- laser, stealth or DRIRE dicing methods
- flip-chip technologies
- multi-layer flex circuit with micro-via
- glass and silicon interposers, 3D packaging.
This presentation aims to give an overview in term of technology maturity level and reliability concerns.
Miromico AG has been developing high-performance I/O's in CMOS technologies for almost 15 years. The application span includes various chip-to-chip communication links, where the ICs are either sitting on the same PCB (C2C) or on different PCBs connected through a backplane (BP).
With the exponential growth of on-chip functionality and high cost of IC pads and interconnections, parallel data exchange is no longer an option for most applications and has been systematically replaced by High Speed Serial (HSS) links. The improvement of Si-technologies, bringing along an ever increasing rate of core processing clocks, continuously sets new targets in terms of I/O bandwidth. New industry standard are being defined at the 32, 56 and 112 Gbps/pad data rates, in order to accommodate the increasing demands of cloud computing and modern data centers.
Design challenges on analog side include the fact that further scaling in IC technologies is no longer accompanied by large gains in intrinsic device speed, so that performance improvement must also come from innovative system design and direct collaboration with technology developers. Furthermore and especially for BP applications, the channel response at the frequencies of interest is typically introducing significant losses and reflections that must be compensated in order to maintain the signal integrity. Adaptive signal equalization, in the continuous- and/or discrete-time domains, becomes a vital integral function in the design of modern I/Os.
The objective of this tutorial is to give a brief overview, spanning from industry trends and marketing requirements down to system solutions and specific analog functions. The focus will be on Physical Layer and full-custom analog/mixed-signal design techniques.