FPC design and testing for the High-Granularity Timing Detector for the Phase II upgrade of the ATLAS calorimeter system

20 Sept 2018, 17:00
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster Systems, Planning, Installation, Commissioning and Running Experience Posters

Speaker

Maria Robles Manzano (Johannes Gutenberg Universitaet Mainz (DE))

Description

The High-Granularity Timing Detector (HGTD) will improve the performance of the ATLAS detector for the Phase II upgrade of the HL-LHC by providing precise timing information. The detector base unit consists of a hybrid module of a 2x4 cm$^2$ Low Gain Avalanche Detector (LGAD) bump-bonded to two ASICs and wire-bonded to a Flexible Printed Circuit (FLEX cable). The latter transmits high-speed signals (1.28 Gbps) for data readout while providing power and HV to the module. Its design must fulfil the HGTD requirements both mechanically and electrically, combining different signal types. Test results of our initial prototype are presented.

Summary

With the High-Luminosity LHC upgrade at CERN, the number of proton collisions (pile-up) per bunch crossing increases significantly. The ATLAS detector will be upgraded to cope with this new scenario. Most prominently the inner tracker (ITk) will be replaced and extended to cover a region up to || < 4. In the endcap regions, at 2.4 < || < 4, additional pile-up rejection will be provided by the High Granularity Timing Detector (HGTD) based on Low Gain Avalanche Detectors (LGADs). By exploiting the time information with 30 ps resolution for a single MIP, the pile-up is effectively reduced by a factor 6. The base unit of the HGTD, a hybrid module, consists of a LGAD (2 x 4 cm2) bump-bonded to two ASICs. This system is glued to a Flexible Printed Circuit (FLEX cable): more than 7000 of these modules will cover the active area of the detector. The FLEX cable’s purpose is to supply the bias voltage to the LGADs, power to the ASICs and includes e-links for data transmission to the peripheral electronics as well as clock and slow control signals. The very harsh requirements on the FLEX cable include limited thickness and width (300 m and 2 cm, respectively), good insulation of the electrical lines, with HV up to 1kV, radiation hardness and operation at -30 C. In order to test the performance of the FLEX cable, a prototype was designed at the University of Mainz and produced by Schoeller Electronics Systems GmbH. It has a length of 750 mm, corresponding to the maximal distance of a module to the peripheral electronics and it includes a representative set of signals: high-speed differential pairs (1.28 Gbps, SLVS), input clocks (320 MHz, LVDS), power signals (VDDD and VDDA) and a high voltage line. The prototype’s aim is to understand the technology requirements (materials, manufacturing capability, electrical and mechanical robustness) and to address potential problems by including a significant subset of the signals (signal integrity, power distribution, HV-insulation, interference and crosstalk). To evaluate the performance of the FLEX, the following tests are performed:
1. Insulation of the HV line up to 1 kV.
2. Integrated Bit Error Test using a Kintex KC705 Evaluation Board for bit pattern generation. A custom adapter board was designed to connect the FLEX cable to the evaluation board.
3. Time Domain Reflectometry to measure the impedance of the tracks and the matching with the reference value of 100 Ω, which is crucial for the high-speed data transmission.
4. Temperature dependence of the performance by repeating the above tests in a climate chamber.

Primary author

Maria Robles Manzano (Johannes Gutenberg Universitaet Mainz (DE))

Co-authors

Andrea Salvatore Brogna (Johannes-Gutenberg-Universitaet Mainz (DE)) Kurt Atila (Johannes Gutenberg Universitaet Mainz (DE)) Prof. Lucia Masetti (Johannes Gutenberg Universitaet Mainz (DE)) Dr Quirin Weitzel

Presentation materials

Peer reviewing

Paper