Conveners
Posters: Posters session - 1 Programmable Logic, Design Tools and Methods
- Ken Wyllie (CERN)
Posters: Posters session - 1 ASIC
- Ken Wyllie (CERN)
Posters: Posters session - 1 Optoelectronics and Links
- Ken Wyllie (CERN)
Posters: Posters session - 2 Other
- Ken Wyllie (CERN)
Posters: Posters session - 2 Production, Testing and Reliability
- Ken Wyllie (CERN)
Posters: Posters session - 2 Systems, Planning, Installation, Commissioning and Running Experience
- Ken Wyllie (CERN)
Posters: Posters session - 2 Trigger
- Ken Wyllie (CERN)
Posters: Posters session - 2 Power, Grounding and Shielding
- Ken Wyllie (CERN)
Posters: Posters session - 2 Radiation Tolerant Components and Systems
- Ken Wyllie (CERN)
We present the design and performance of PSEC4A: an 8-channel, 10 GSa/s switched-capacitor array waveform sampling and digitizing ASIC, which incorporates multi-event buffering to reduce deadtime induced latency for close-in-time triggers. The PSEC4A chip uses a primary sampling array of 132 sampling capacitors that can be written to a bank of 1056 storage capacitors segmented in 8 randomly...
The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (PLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude...
This paper presents a Fast-Tracker front-end (FTfe) for small-diameter Muon Drift Tube (sMDT) detectors at future hadron colliders. The design addresses the higher background rate capability required by the sMDT detectors, which needs to be complemented by suitable front-end electronics. sMDT chambers operate at short maximum drift time and, consequently, short dead-time, maximizing the muon...
The concentrator integrated circuit (CIC) is a front-end chip for both PS and 2S modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream FE chips (either MPAs or CBCs) format and transmit it to the LpGBT unit. The design and implementation in a 65nm CMOS technology of the first prototype are presented.
Recent analog to digital converters with the successive approximation (SAR ADC) are popular for high speed, low power operation, and accuracy. SAR ADC demands a precise internal digital to analog converter (DAC) which is mostly made using capacitors. This article presents two new approaches how to design the capacitor DAC in 180 nm SOI technology. The first is 10-bit split DAC and the second...
The HRFlexToT is a 16-channel ASIC for SiPM anode readout designed for Positron Emission Tomography (PET) applications that features high dynamic range (>8 bits), high speed and low power (~3,5 mW/ch). The ASIC has been manufactured using XFAB 0,18 µm CMOS technology. Initial measurements show a linearity error below 3%. Single Photon Time Resolution (SPTR) standard deviation measurements...
FEEWAVE is an ASIC designed for Multi-gap Resistive Plate Chamber (MRPC) for good time resolution. As a highly integrated chip, the ASIC includes front-end circuit, waveform sampler, and analog-digital conversion. The chip implements Time over Threshold (TOT) function and waveform digitization. It has high speed sampling rate (5 GS/s) and high trigger rate capability (50 kHz). The ASIC is...
We present a low-noise Charge-Sensitive Amplifier (CSA) manufactured in a standard 0.35μm CMOS process. The CSA is part of an integrated sensor named Topmetal-S, with an array of which, forms a charge readout plane in a high-pressure gaseous TPC for 0νββ search. A single-ended folded cascode amplifier with a 73dB open-loop gain and 340MHz gain-bandwidth product forms the main amplification...
For the ATLAS Phase-II upgrade, a complete new all-silicon inner tracker is planned, which will be readout at higher bandwidth due to finer granularity and higher occupancy.
While both subdetectors allow the usage of the GBT protocol on the downlink path, ITk Pixel needs a different uplink protocol due to the constrains given.
This work shows how a detector specific extension of the FELIX...
A pixel chip based on the Hit-Driven scheme was designed for the HEPS project in China. The full information of every photon, including the hit position, arrival time, and photon energy, are detected by the ToT method. Thus a 3D animation of clusters can be rebuild. Priority arbitrary logic was designed to readout all the hit pixels sequentially to the column FIFO, and the chip overall buffer....
We present a high resolution sigma-delta ($\Sigma\Delta$) Analog-to-Digital Converter (ADC) manufactured in a 0.35 $\mu$m CMOS process. The ADC consists of a cascaded $\Sigma\Delta$ modulator and a SINC4 decimation filter. Tests show that the ADC achieved a 80 dB signal-to-noise ratio and a 14 effective number of bits with a 25.6 MHz sampling clock at a 200 kHz input signal. Its...
High data rate requirements of the CMS Outer Tracker front-end electronics in the High-Luminosity LHC and the optimum utilization of the optical link bandwidth necessitate the development of a data aggregator ASIC; namely Concentrator IC (CIC).
To facilitate the RTL code development and to allow functional verification of the CIC ASIC in the context of the entire readout chain, a simulation...
We present the design and characterization of a high performance resistance measurement circuit fabricated in a standard 0.35μm CMOS process. The circuit implements two exposed metal electrodes in the topmost metal layer which can be deposited the sensitive thin-film. Test pulse is injected into one electrode, the other electrode is directly fed into a low noise charge sensitive amplifier with...
The design of a single particle counter for therapeutical proton beams based on Low Gain Avalanche Diodes (LGADs) optimized for very fast signals is carried on in the framework of the INFN MoveIt research project. Fast signal shaping front-end electronics is mandatory in this application in order to deal with particle rates of the order of hundreds of MHz. Two preamplifier architectures, one...
This work discusses four different algorithms for the minimization of threshold dispersion in multichannel readout circuits for pixel detectors. These algorithms, which are based on different methods (e.g. charge scans, threshold scans, etc) and differs in terms of performance and computation time, have been tested on the asynchronous front-end integrated in the CHIPIX65_FE0, a readout ASIC...
The readout system for the upcoming Run3 upgrade of the LHCb experiment at CERN is based on a common readout board called PCIe40. This common FPGA-based board can be reconfigured to serve different subsystems within LHCb. A CI/CD pipeline was implemented in order to automatically cross-validate the tight interaction between our custom FPGA firmware and the associated DAQ and control software,...
In this work an experimental high-energy radiation sensor is presented which is based on an SRAM (Static Random Access Memory). The radiation flux is measured with the memory by counting the number of Single-Event Upsets (SEUs) within one readout cycle. This monolithic sensor allows a cheap alternative to existing sensors . The SRAM has a refresh rate of 100Hz with 20480 bits. The core supply...
With future pixel ASICs trending towards mega-frame rate readout, the development of ultra-high-speed readout systems is increasingly important. Here we present an ultra-fast readout system developed to operate at 10Gb/s, and intended to surpass a more conventional highly-parallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles and serialises the parallel input...
The lpGBT is a 10 Gbps transceiver ASIC meant to be used in High Luminosity LHC detectors.
It provides a variety of communication interfaces, including multi-mode high-speed serial interfaces, I2C, and parallel IO.
The Universal Verification Methodology had been selected to verify chips design and implementation.
This paper discusses the strategies used to verify all the chip functionalities,...
This work describes several applications where an 8-channel enhanced Multiple Use SiPM Integrated Circuit (eMUSIC) ASIC for SiPM readout can be used to replace PMTs. Several SHiP (Search For Hidden Particles) Experiment Detectors at CERN SPS (Super Proton Synchrotron) are studying the employment of eMUSIC for the ToF (Time-of-Flight) Timing Detector with timing resolution around 100 ps....
Readout electronics for modern particle imaging based identification detectors must be compact, low power, deliver acceptable timing resolution and be robust to pile-ups. The solution is to integrate full waveform sampling, analog buffering and feature extraction and digital signal processing into one single Application Specific Integrated Circuit (ASoC in the following). ASoC can be used as a...
We report on the latest developments of a silicon photonic optical transmission system based on wavelength division multiplexing (WDM) for high-speed links in detector instrumentation. The essential component is a monolithically integrated multi-wavelength transmitter based on depletion-type pn-modulators. Based on our designs, a photonic transmitter chip has been fabricated. We present...
In order to satisfy the high output bandwidth requirement imposed by the HL-LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the HL-LHC pixel detector. A CDR/PLL circuit recovers clock from the 160 Mbps incoming data, and provides high speed clock to the serializer, where the 1.28 Gbps output stream is formed. The output stage employs a...
The New Small Wheel (NSW) is an upgrade for enhanced triggering and reconstruction of muons in the forward region of the ATLAS detector at CERN's LHC. The NSW will compose two detector technologies: Micromegas (MM) and small-strip Thin Gap Chamber (sTGC). Both detectors will be used for muon triggering at the first-level trigger and for precision tracking. Four custom-designed ASICs are...
The CLIC Tracker Detector (CLICTD) is a monolithic pixel sensor chip targeted at the tracking detector of the Compact Linear Collider (CLIC). The chip features a matrix of ${16\times128}$ cells, each cell measuring ${300\times30}$$\mu m^{2}$. The cells are segmented in the long direction in order to maintain the benefits of the small collection electrode. In the digital logic, a simultaneous...
High Voltage CMOS (HVCMOS) pixel sensor ASICs are engineered to meet the requirements of ATLAS ITk pixel barrel outer layers for LHC high luminosity upgrade. This work presents the design of HVCMOS sensor ASICs with emphasis on the readout system architecture and Digital Control Unit (DCU) design. The on-chip readout system introduces an efficient data transfer scheme from pixels to chip...
Following the necessity to replace the front-end electronics of the ATLAS Monitored Drift Tube chambers, the new MDT-ASD2 ASIC has been developed and tested. The ASD2 comes as a replacement for the original octal Amplifier/Shaper/Discriminator optimized for the MDT-chamber readout for HL-LHC. The ASIC is made in IBM 130nm CMOS technology and provides superior chip-to-chip and...
The Ethernet network is a good control interface for distributed measurement systems.
The de facto standard in HEP experiments is IPbus. The experiences from using IPbus resulted in the proposal of a new Ethernet-based control interface optimized for quick parallel configuration of multiple systems.
The system ensures reliable delivery of control commands and responses.
The minimalistic local...
A FPGA based time measurement electronics is developed for MRPC (multigap resistive plate chamber) detector in TOF (time of flight) applications. The basic structure is composed of an ultra-fast amplifier/discriminator (NINO) connected to MRPC and a dedicated FPGA based time-to-digital converter to measure TOT (Time-Over-Threshold), instead of charge. Preliminary tests show that the RMS of...
CMOS Pixel Sensors have been used in subatomic physics experiments for tracking devices. There are large quantities of hits generated by particles that coming from the detector beam background impacting tracking efficiency and reducing system bandwidth. We propose to design a CMOS pixel sensor with on-chip Artificial Neural Network (ANN) to tag and remove hits generated by background particles...
The Data Processing Boards (DPB) are the important component of the development version of the CBM readout system. Even though in the final version they will be replaced with the new Common Readout Interface (CRI) PCIe boards, they are still used for development and testing of new firmware features and for operation during the beam tests.
The paper describes the current state of the DPB...
This talk will present the results of in-situ measurements of radiaton damage for the on-detector optoelectronics for the ATLAS SemiConductor Tracker. The results come from proton-proton collisions in LHC during operation in 2016 and 2017. Both p-i-n diodes and VCSELs will be presented and compared to expectations from beam tests of identical devices before the start of LHC operation. The...
At the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, the double-sided silicon strip sub-detector of the Belle II experiment is read out by 1748 APV25 chips.
FPGAs perform several calculations on the digitized signals. One of them is "Hit Time Finding": the determination of the time and amplitude of the signal peaks of each event in real time using pre-programmed neural...
Commercial-off-the-shelf photonic components do
not satisfy the requirements of typical spacecraft or particle-physics detector applications. In order to reduce
costs and schedule risk for insertion of photonic components into these harsh-environment applications,
we developed single- and multi-channel ruggedized photonic transceiver modules and active optical
cables for aerospace, particle...
The Mu3e experiment is searching for the charged lepton flavour violating decay $\mu^{+} \to e^{+}e^{-}e^{+}$. The core elements of the detector are High Voltage Monolithic Active Pixel Sensors (HV-MAPS).
The actual status of development and testing will be presented together with the latest test version of the chip. This version, the MuPix9, takes into account the testing results of the...
High speed links are commonly used in High Energy Physics experiments for data acquisition, trigger and timing distribution. For this reason, a radiation-hard link is being developed in order to match the increasing bandwidth demand of the backend electronics and computing systems. In this framework, the LpGBT -which is the evolution of the GBTx SERDES- is being designed and is foreseen to be...
Due to challenging conditions of the HL-LHC, the CMS detectors are undergoing a system-wide upgrade, and specifically the complete redesign of the end cap sub-detectors.
To reach the aimed resolution of 30 ps RMS on events timing information, a precision clock distribution system providing a readout clock with a sub 15 ps RMS jitter is necessary.
In this talk, a detailed study on the current...
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to exploit new physics beyond the Standard Model. The readout ASIC is required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us...
The strategy for beam setup and machine protection of the accelerators at the European Organization for Nuclear Research (CERN) relies strongly on their Beam Loss Monitoring (BLM) systems, which are currently being renovated. The main acquisition path has shown very promising results, and development is now concentrated to provide advanced remote diagnostics, setup and monitoring features. In...
Time of arrival measurement using the constant discrimination technique built upon continuous switched capacitor sampling of an input waveform with a precise and high frequency clock or with a bucket-brigade-type integrated MOS analog delay line for producing a delayed version of the input signal is presented. The concepts are laid out and analyzed. The relation between the sampling or...
We present the quality assurance (QA) test of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld and a low-latency, low-overhead dual-channel transmitter ASIC LOCx2 for the ATLAS Liquid Argon Calorimeter Phase-I upgrade. In the QA test, we screen about 7200 LOCld chips and 7200 LOCx2 chips to ensure their basic functionality. All tests are automatically conducted...
The Read-Out Controller (ROC) ASIC will be used to store, de-randomize, aggregate, filter and form complex packets with the digitized data coming from the New Small Wheel (NSW) muon detectors of the ATLAS experiment. The ASIC test setup is based on a Xilinx Kintex Ultrascale FPGA evaluation board, implementing input data streams emulators and output data analyzers for functional verification...
We present the readout and data transmission of a MAPS prototype MIC4 for the R&D of the CEPC vertex detector. New data-driven readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. MIC4 contains a matrix of 128 rows by 64 columns with a pixel pitch of 25 μm. By a periphery priority encoder circuit and a data readout and framing...
The miniaturised optical transceiver module, developed in the framework of the Versatile Link PLUS project (VL+) will be installed in the upgraded detector front-ends at the HL-LHC. The modules will have to operate over a wide temperature range (-35 °C to +60 °C). We describe the impact of the temperature on the performance of the transceiver and we present simulation and measurement results...
Current existing alpha/beta counters use gas-flow detectors becasue of their low energy detection threshold compared to Passivated, Implanted, Planar Silicon (PIPS®) detectors. However, gas based systems suffer drawbacks with respect to safety and required infrastructure for the gas. The latest evolutions of the characteristics of PIPS® detectors allow to reach a lower energy threshold, that...
Single muon triggers are crucial for the physics programmes at hadron collider experiments. To keep the trigger rates reasonable low they must be highly selective.
Muon system at LHC experiments and at future colliders use two muon chamber system for triggering. Fast trigger chambers, identifying the bunch crossing and providing a course momentum estimation, and slower precision chambers, for...
We propose a novel fast track finding system capable of reconstructing four dimensional particle trajectories in real time using precise space and time information of the hits. The fast track finding device that we are proposing is based on a massively parallel algorithm to be implemented in commercial field-programmable gate array using a pipelined architecture. We will present studies of...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate. Simulation of the on-detector electronics based on a trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first...
The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the HL-LHC upgrade around 2025. The read-out of the ITk pixel system will be most challenging in terms of data rate. First test of read-out concepts are performed with the ITk Pixel “demonstrator”, a system composed of several ITk-style modules with in total 120 FE-I4 read-out chips. Their read-out is...
We have developed an updated DaughterBoard design for control and readout of the upgraded ATLAS hadronic Tile Calorimeter electronics for HL-LHC. The new design migrated from two QSFPs to four SFP+ modules handling: 4×9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and 2×4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT...
Single Event Effects introduce soft errors in ASICs. Design methodologies like Triple Modular Redundancy (TMR) with clock skew insertion, a system level redundancy technique is a common practice by designers to mitigate soft error rates. However, the optimal spacing between memory elements in a TMR in 65nm process hasn't been addressed so far. RD53SEU is a mini ASIC development under the...
The CMS Drift Tubes (DT) readout system has been upgraded during the 2017-2018 technical stop to a new uTCA-based system (uROS) to deliver the performance required by the increase of LHC luminosity. It comprises 3 uTCA crates with up to 25 boards, each processing 3 sectors from each CMS wheel. The uROS board is built around a Virtex-7 FPGA, and is able to receive 72 input links. The 240-Mbps...
CMS ECAL Phase2 Front-End(FE) card is designed to provide streaming of the data generated on the Very-Frond-End(VFE) cards to the back-end electronics. FE card will use the components developed within the VersatileLink project. It will contain four or six lpGBT ASICS with corresponding VersatileLink+ optical modules. Prototype FE card was developed to validate the clock distribution, high...
This paper proposes a 1 GHz Delay Locked Loop (DLL) which was processed in a 65 nm CMOS technology. The circuit was designed for harsh environments, in particular ionizing radiation. It has a single event recovery time of less than 1 us. The DLL is used inside a Time to digital converter (TDC), and achieves an rms jitter below 800 fs. One of the improvements to this low jitter comes from the...
We present the Detector Control System (DCS) system being designed for triple-GEM detectors to be installed in 2019-2020 in the CMS muon endcaps for HL-LHC. Beginning of 2017, 10 triple-GEMs, called slice-test, have been installed for the very first time in CMS. Therefore the GEM DCS had basically to be designed from scratch. We will describe its key features (hardware and software), the main...
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground Neutrino experiment with a 20-thousand-ton liquid scintillator detector at 700-meter deep underground. All the signals coming from the almost 18000 Central Detector 20-inch photomultipliers (PMTs), will be digitized thanks to high-speed high-resolution waveform full sampling technique. An Analog to Digital...
Jiangmen Underground Neutrino observatory (JUNO) is a neutrino medium baseline experiment in construction in China, with the main goal to determine the neutrino mass hierarchy. A large liquid scintillator (LS) volume will detect the antineutrinos issued from nuclear reactors. The LS detector is instrumented by around 20000 large photomultiplier tubes. The JUNO electronics readout system...
A trigger processor demonstrator card has been designed for the CMS Barrel Muon Trigger (BMT) upgrade at HL-LHC. A two-layer system design is foreseen for BMT. Layer-1 hosts the trigger primitive algorithms and preliminary tracking algorithms. Layer-2 hosts the main track finding algorithm, the correlation between the tracks from the muon system and the track-trigger for best possible estimate...
Considerable enhancements are foreseen for the Drift Tubes (DT) subdetector during Phase-2 CMS upgrade. The new HL-LHC CMS Trigger/DAQ requirements exceed the present capabilities of the on detector electronics (MiniCrate). Therefore, as a consequence of the higher L1A rate set by CMS, as well as MiniCrate maintainability and chamber aging mitigation arguments, all MiniCrates will be replaced...
The ATLAS Experiment will upgrade its Inner Tracking system for the High-Luminosity-LHC with an all-silicon system. The strip part will be based on individual modules, constructed by gluing the front-end hybrids directly onto the strip side of the sensors. The modules will then be glued onto a low-mass local support core with services integrated. We have constructed the first double-sided...
The High-Granularity Timing Detector (HGTD) will improve the performance of the ATLAS detector for the Phase II upgrade of the HL-LHC by providing precise timing information. The detector base unit consists of a hybrid module of a 2x4 cm$^2$ Low Gain Avalanche Detector (LGAD) bump-bonded to two ASICs and wire-bonded to a Flexible Printed Circuit (FLEX cable). The latter transmits high-speed...
The ATLAS Experiment will upgrade its tracker with an all-silicon Inner Tracker (ITk) for the HL-LHC, comprising pixel and strip detectors. The strip detector is based on silicon strip sensors, which are read out by low mass radiation-hard circuits carrying custom designed radiation-hard ASICs in 130 nm technology. The circuits are made from flexible PCB multi-layer copper polyimide...
The CMS Outer Tracker planned for the HL-LHC Upgrade contains strip-strip and pixel-strip silicon modules. Each of them includes two high-density front-end hybrid circuits, equipped with flip-chip ASICs, passives, connectors and mechanical structures. Several strip-strip hybrid prototypes have been produced using the CBC2 front-end ASIC. Feedback from these developments helped improving the...
A fast continuously sampling digitiser have been designed for acquiring the signal from LaBr3 scintillating crystals detectors. They are foreseen in the FAMU experiment, aimed at spectroscopic measurements of muonic hydrogen, possibly providing insights into proton radius puzzle. The board, named GSPS, is an FMC mezzanine which hosts two off-the-shelf sampling ADC used in interleaved timing...
We present a new kind of silicon device: a High-Voltage vertical JFET, conceived as a candidate for the High-Voltage Multiplexing switch in the ATLAS upgrade of the silicon microstrip Inner Tracker (ITk). Both n-type and p-type HV-JFETs have been successfully fabricated in the silicon processing facility of Brookhaven National Lab. Probe station measurements of un-irradiated devices show low...
Radiation-hard, compact, low-mass, hybrid GaN and CMOS integrated module DC-DC converter has been designed. The converter has an input voltage of up to 18V regulated down to an output voltage of 1.5V, with 7A maximum load current. It exhibits >70% efficiency. Discrete GaN transistors are used for the power stage, and the controller circuitry and power device drivers are integrated on a 0.35um...
The Fast Tracker(FTK) is an integral part of trigger upgrade program for
the ATLAS experiment. At LHC Run2, which started operation in June 2015
at a center-of-mass energy of 13 TeV, the peak luminosity has exceeded $2×10^{34}
cm^{−2}s^{−1}$ and the LHC produce an average of 60 simultaneous collisions.
The higher luminosity demands a more sophisticated trigger system with
increased use of...
During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out the front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). This work will present the irradiation campaigns performed on the V2, V3 and V4 prototypes of the SAMPA chip. The irradiation campaigns have been performed...
The Level-1 Data Driver Card (L1DDC) was designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. L1DDC is a high speed aggregator board capable of communicating with multiple front-end electronic boards. It collects the Level-1 data along with monitoring data and transmits them to a network interface through bidirectional and/or...
This work presents an automated solution for testing medium scale ASIC productions. Small scale prototype ASIC production are tested by hand in order to validate ASIC designs, and big scale ASIC productions are validated using industrial methods either checking directly the wafer or using specific instrumentation. Scientific experiments usually require producing thousands of ASICs that do not...
In order to save the space in the underground counting rooms during the ATLAS phase II upgrades, a project dedicated to the study of the impact of taller rack integration in the actual counting rooms was launched analyzing its cooling performance and the impact on the cooling infrastructures.
A new 63U prototype rack equipped with three ATCA shelves with open bottom to top airflow, high power...
To face the harsh environmental conditions in high energy physics, the systems have to find the right balance between high availability and fault tolerance. In response to the new failures during the runs, the graceful degradation has to be adaptive, with the minimum of impact on the data acquisition chain. To improve the Trigger Concentrator Cards, during the CMS Level-1 trigger upgrade, the...
Linear array detectors with high spatial resolution and MHz frame-rates are essential for high-rate experiments at accelerator facilities. We have developed KALYPSO, a line array detector with 1024 pixels operating at 10 Mfps. To improve the spatial resolution and sensitivity at different wavelengths, novel Si microstrip sensors have been developed with a pitch of 25 µm. Furthermore, to enable...
Time response of a Silicon Photomultiplier (SiPM) depends on some of the intrinsic parameters of the sensor. Combining multiple small SiPM instead of one with larger area will reduce detector capacitance at electronic level, which can be translated into a lower jitter, and thus better Coincidence Time Resolution (CTR) of a PET system. This work provides a framework by combining GATE and an...
The Mu2e electromagnetic calorimeter is composed of un-doped CsI crystals coupled to large area Silicon Photomultipliers (SiPMs). A custom SiPM layout consisting of 2 series of 3 6x6 mm^2 UV-extended monolithic SiPMs has been developed. So far, the production of 4000 pieces is ongoing and a detailed Quality Assurance (QA) process is being carried out on each monolithic SiPMs with an...
The Ring Imaging Cherenkov detectors are key components for particle identification in LHCb experiment at CERN. The present RICH photodetectors will be replaced by multi‐anode photomultiplier tubes and front‐end electronics capable of operating at a 40MHz input rate. About 33.000 CLARO8 packaged ASICs have been manufactured and tested on a dedicated automatic pick‐and‐place station. About 4200...
The readout board for the ALICE TOF detector named DRM2 is now in the production phase: 88 boards are being produced (72 are needed in the experiment). Since the board will operate in a radiation environment (0.13 krad total dose expected in 10 years), a complete irradiation campaign at the component level was performed. We will focus on the Microsemi Igloo2 FPGA and two Avago optical...
Vacuum in the ARCs of the LHC is crucial to minimize beam – gas interactions and to assure thermal insulation of cryostats and helium distribution lines. Several hundred of sensors with their associated conditioning electronics are installed across the ARCs for both beam and insulation vacuum measurements. Simulations predict that radiation levels will greatly increase during HL-LHC era....
Real-time track reconstruction in high energy physics experiments at colliders running at high luminosity is very challenging for trigger systems. To perform pattern-recognition and track fitting, artificial Retina or Hough transformation algorithms have been introduced in the field which have usually to be implemented in the state of the art FPGA devices. In this paper we report on simulated...
The CMS experiment implements a sophisticated two-level triggering system composed of hardware-based Level-1, and a software-based High Level Trigger. A new Level-1 trigger architecture improves the performance at high luminosity experienced during Run II. The upgraded muon trigger combines information from the three muon detectors - Cathode Strip Chambers (CSC), Drift Tubes (DT) and Resistive...
The CMS ECAL barrel electronics will be upgraded for the HL-LHC to comply with increased latency and bandwidth requirements of the Level 1 trigger, to preserve detector performance despite the increased instantaneous luminosity, and to provide a precision timing measurement in addition to energy. The chosen solution includes a custom dual gain trans-impedance amplifier implemented in a 130nm...
The Embedded Local Monitor Board (ELMB) is a microcontroller based plug-in module with CANopen communication protocol. It has been widely used in LHC systems and experiments for slow-control and monitoring purposes, providing multiple galvanically isolated analog and digital inputs and outputs.
While these modules have shown excellent performance in the past 15 years, a replacement is...
The second generation of the 8 channel PaDiWa-AMPS front-end board was recently assembled at the GSI department for Experiment Electronics (GSI EE). The board implements precise TDC and QDC measurements optimized to read out the 978 PMTs of the HADES electromagnetic calorimeter (ECAL). The HADES ECAL detector is currently under commissioning. In this contribution the read-out scheme of the...
The ATLAS experiment at the LHC is undergoing a major upgrade to handle the higher collision rate that will be provided by the High-Luminosity LHC. A major component of the ATLAS Phase-II upgrade is the Inner Tracker, an all-silicon detector featuring novel n+-in-p microstrip sensors. Miniature sensors implementing this design are tested for their radiation tolerance at the upgraded...
The WaveCatcher systems are a family of powerful and low cost digitizers. Their number of channels ranges between 2 and 64. They easily replace oscilloscopes in numerous applications. They are based on the SAMLONG ASIC which samples the signal between 400 MS/s and 3.2 GS/s over 12 bits with a bandwidth of 500 MHz.
The systems can also be used as TDCs for high precision time measurement....
The CMS High Level Trigger has been designed to run a streamlined version of the offline reconstruction software on a traditional computer farm. To address the challenge presented by the Higher Luminosity-LHC, CMS is evaluating a heterogeneous computing platform for the HLT, aiming to deploy a prototype in production already during Run 3. The R&D work on the software framework and...
Currently, various hardware concepts and technologies are being evaluated for the CMS Phase 2 Tracker off-detector processing system. The back-end electronics system comprises the Data Trigger and Control (DTC) system, the Track Finding Processors (TFP) and the DAQ \& TTC Hub (DTH). We designed UltraFlex as an ATCA based technology demonstrator with two main purposes: to implement a flexible...
