An Ultra-Fast 10Gb/s 64b66b Data Serialiser Back-end in 65nm CMOS Technology

18 Sept 2018, 17:20
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster ASIC Posters

Speaker

Mr Thomas Gardiner (STFC)

Description

With future pixel ASICs trending towards mega-frame rate readout, the development of ultra-high-speed readout systems is increasingly important. Here we present an ultra-fast readout system developed to operate at 10Gb/s, and intended to surpass a more conventional highly-parallel LVDS bus approach. The system generates a 5GHz clock (LC Oscillator), scrambles and serialises the parallel input data in accordance with the Aurora 64b66b protocol, and transmits the data off-chip through a Current Mode Logic (CML) line-driver at 10Gb/s. A prototype is under evaluation having been fabricated in early 2018 on a 65nm Multi-Project Wafer. The results from testing are reported.

Summary

Our prototype 10Gbps readout system has been developed as a potential solution to near-future pixel detector readout requirements of 1 mega-frames plus. As an example of the scale of the challenge faced, the readout of a 200 by 200-pixel ASIC with each pixel digitalised to 10b would equate to a data throughput speed of 400Gb/s for a 1MHz frame rate. In a LVDS readout system rated at 1Gb/s per link, 400 LVDS links and 800 IO pads would be required, compared to only 40 10Gbps serializer modules and 80 IO pads.
Designed in 65nm CMOS, the readout system makes use of the fast short-channel devices to achieve the required high speeds, and an integrated inductor for the generation of a 5GHz clock. Data is input to the system via an asynchronous FIFO to manage the transfer of data between the clock domain of the pixels and that of the high speed readout system. The FIFO provides its own empty and full flags, so in the event that no data is available, the readout system will detect this and automatically send out a predefined idle packet compliant with the Aurora 64B66B specification, and providing a constant flow of pseudo dc-balanced data as required for ultra-fast communication.
A 64-bit data packet is collected from the FIFO and divided into 8-bit packets that are input in series into a mixed signal Aurora 64b66b compliant scrambler operating at 1.25GHz. Scrambled data is delivered to the serializer in 8-bit words with each bit incrementally time-shifted by 100ps. The serializer contains self-developed custom sync circuitry and True Single Phase Clock (TSPC) flip-flops for 5GHz operation. Serialised data is finally transmitted off-chip through a CML driver at 10Gbps. The circuit board tracking and bond wires were modelled and simulated using a number of tools to obtain accurate parasitic estimates.
The design has been fabricated on a 65nm Multi-Project Wafer alongside other prototype circuits, and subsequently wire-bonded to a custom Printed Circuit Board (PCB) for evaluation. A Texas Instruments 10Gbps re-timer chip is included on the PCB to diagnose and re-buffer the 10Gbps link for off-PCB communication. For evaluation of the design, the assembled PCB has been connected to a Xilinx 7 series FPGA using a HPC FMC bridge and the Aurora 64b66b transceiver IP.
We will present the results from electrical characterization, and outline our plans for future developments.

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