An integrated SRAM radiation monitor in 180 nm CMOS technology

18 Sept 2018, 17:20
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster Radiation Tolerant Components and Systems Posters

Speaker

Jeffrey Prinzie (KU Leuven (BE))

Description

In this work an experimental high-energy radiation sensor is presented which is based on an SRAM (Static Random Access Memory). The radiation flux is measured with the memory by counting the number of Single-Event Upsets (SEUs) within one readout cycle. This monolithic sensor allows a cheap alternative to existing sensors . The SRAM has a refresh rate of 100Hz with 20480 bits. The core supply voltage of the memory can be lowered to increase the SEU sensitivity. The sensor was verified experimentally with heavy ions, protons and two-photon laser tests.

Summary

Radiation monitoring is required in any nuclear facility like nuclear power plants, high-energy physics experiments but also for space and ground applications. Typically this involves expensive sensors and a combination of different technologies to perform the monitoring. SRAM memories have proven useful to monitor ionizing radiation through the measurement of SEUs in the devices. By counting the amount of upsets, an estimation can be made about the particle flux. The measurements may not be as accurate as other dose or dose rate measurements but this approach becomes very cost efficient. Over the past decades, the soft error rate in commercial SRAM devices has been reduced significantly through error coding, which was required to counteract the intrinsic single-event sensitivity of devices in scaled technologies. By developing a custom SRAM ASIC, the increased sensitivity of the scaled devices can be employed to obtain a sensitive memory based radiation sensor.
The ASIC presented in this work was designed and processed in a 180 nm CMOS technology. The memory uses a matrix of custom designed 6 transistor SRAM cells with a cross section of 1.6 µm². The memory is organized as a 16 bit register file with an 11 bit row decoder and 3 bit columns. Each read or write cycle involves the access of 16 bits at once. The row- and column decoders are synthesized with triple-modular redundancy and the address and data can be accessed through a serial interface. The memory can be refreshed at a rate of 100 Hz.
The SRAM consists of 2 power domains and IO voltages. A constant core voltage of 1.8 V is fed to the decoders, read/write logic and serial interface. A second core voltage of 1.8 V is fed to the SRAM array which consists of 20480 SRAM cells. The periodic measurement of the radiation flux consists of three phases, in a first phase, the SRAM can be optionally pre-set to an initial value. During the second phase, the voltage of the SRAM core is reduced to increase the sensitivity to ionizing particles. In the last phase, the core voltage is increased to its nominal value during the readout of the memory. During post-processing, a bitwise XOR operation will show all SEUs in the memory. The first step can be omitted if the previous state of the memory is stored.
The adjustable core voltage of the SRAM array allows the memory to be adjusted in terms of sensitivity. This can be useful if the particle energy is not sufficient to introduce an SEU on the cells. An experimental verification of the sensor has been done with heavy ions, 24 GeV high-energy protons, mixed field radiation and two-photon laser absorption tests for different supply voltages. The heavy ion tests shown a significant increase of the cross section while adjusting the supply voltage. The memory was processed in a 65 nm CMOS technology.

Primary authors

Jeffrey Prinzie (KU Leuven (BE)) Sam Thys (Mirion Technologies) Mr Bjorn Van Bockel (KU Leuven (BE)) Jialei WANG (KU Leuven) Paul Leroux (KU Leuven (BE))

Presentation materials

Peer reviewing

Paper