High-Voltage Silicon JFET for HV Multiplexing for the ATLAS MicroStrip Staves

20 Sept 2018, 17:00
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster Power, Grounding and Shielding Posters

Speaker

Dr Gabriele Giacomini (Brookhaven National Laboratory)

Description

We present a new kind of silicon device: a High-Voltage vertical JFET, conceived as a candidate for the High-Voltage Multiplexing switch in the ATLAS upgrade of the silicon microstrip Inner Tracker (ITk). Both n-type and p-type HV-JFETs have been successfully fabricated in the silicon processing facility of Brookhaven National Lab. Probe station measurements of un-irradiated devices show low leakage current and high breakdown voltage (up to 600V) in the OFF state, and high currents in the ON state. We’ll present for the first time the design, the technology process flow, and the electrical characterization of these devices.

Summary

In the ATLAS ITk upgrade, a few silicon microstrip detectors will be biased together by a single common High-Voltage (HV) line. Failure of one detector which draws a high current would mean switching off the power supply to all the other good detectors in the same stave, thus losing a fairly large detector area, unless the faulty detector is disconnected from the bias line. If a switch that excludes the faulty sensor can be placed between each strip sensor and the common HV line, the other good detectors on the same stave can work normally. The switch must be radiation hard up to 1.2e15 1MeV-neq/cm2, be insensitive to magnetic field, have a breakdown voltage larger than 600V in the OFF state, while it must exhibit a high current in the ON state (especially after irradiation), and preferably be normally ON. These requirements exclude electro-mechanical switches and power MOSFETs, among others. While GaN transistors are the primary choice and have demonstrated excellent performances, at Brookhaven National Lab we conceived a new kind of high-voltage silicon JFET, which – at least before irradiation – satisfies most of these requirements. As well as other silicon power devices, it is based on a vertical structure, where the drain is the silicon substrate. Both n-type and p-type HV-JFETs have been successfully fabricated in a standard planar process in the silicon processing facility of Instrumentation Division at BNL, starting from epitaxial wafers which have been grown according to strict specifications. Before irradiation, at the probe station, they show low leakage currents and high breakdown voltage (up to 600V) in the OFF state, and high currents in the ON state. Irradiation campaigns with protons and neutrons will assess their suitability as rad-hard switches. While at the time of the conference irradiation results may not be available, we’ll present for the first time the design, the technology process flow and the electrical characterization of these devices.

Primary author

Dr Gabriele Giacomini (Brookhaven National Laboratory)

Co-authors

Dr David Lynn (Brookhaven National Laboratory) Mrs Wei Chen (Brookhaven National Laboratory)

Presentation materials

Peer reviewing

Paper