Conveners
Radiation Tolerant Components and Systems
- Philippe Farthouat (CERN)
Radiation Tolerant Components and Systems
- Salvatore Danzeca (CERN)
Radiation Tolerant Components and Systems
- Salvatore Danzeca (CERN)
The H35DEMO is a HV/HR-DMAPS large area chip fabricated in AMS 350nm HV-CMOS technology. It includes two monolithic matrices with pixels of $50\times250\mu m^2$ with analog electronics embedded in a Deep N-WELL also acting as collecting electrode.
Chips were irradiated with both protons and neutrons up to the radiation doses expected for the outermost layers of the ATLAS pixel detector at...
The nSYNC is a radiation tolerant custom ASIC, developed in UMC 130 nm technology for the readout electronics upgrade of the LHCb Muon System. The chip will be exposed, over ten years of operation, to a total dose of 130 Gy and fluence of 2 · 1012 cm−2 1MeV neutrons equivalent. We present the results of radiation tests performed at the Catana facility (INFN, LNS) with 60 MeV protons beam, up...
One of the challenges facing the system-level design of the ATLAS ITk Strip Detector is the understanding of the TID induced leakage current in the chosen 130nm CMOS technology. The effect of ionizing radiation on the current increase of the ABC130 readout ASIC has been studied at various different dose rates and temperatures using x-ray tubes and Co-60 sources. In addition, the efficacy of...
The LHC planned two phases of upgrades to improve the instantaneous luminosity. An accompanying upgrade of the readout electronics for the ATLAS detectors is planned to handle the increased trigger rates and readout data bandwidth. Due to high flexibility and short development-cycle, FPGA-based systems are increasingly popular within the high-energy physics community. We present here a...
Considered as a back-up solution of the upgraded LHCb RICH sub-detectors, the antifuse FPGAs have been seen as a viable solution to be used in the harsh radiation environment of high energy physics and space experiments. This study is a summary of test beam results performed on a 0.15 µm CMOS antifuse device with a proton beam. We are characterizing the FPGA behavior under large TID and high...
This paper presents the results of a Single Event Upset (SEU) test with heavy ions on a shift register manufactured in a 28nm commercial CMOS technology, interesting for future upgrades for HL-LHC. Results will show the cross section curve in a Linear Energy Transfer (LET) range between 3-60 MeV∙cm^2/mg for different patterns.
