Conveners
ASIC
- Grzegorz Deptuch (Fermi National Accelerator Lab. (US))
ASIC
- Jorgen Christiansen (CERN)
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
ASIC
- Wladyslaw Dabrowski (AGH University of Science and Technology (PL))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Gui Ping
The first prototype of the full-size, full-functionality Macro Pixel ASIC has been prototyped in a $65\,nm$ technology employing radiation tolerant techniques. It is a pixel readout ASIC designed for the Phase-II upgrade of the CMS Outer Tracker detector. It features novel on-chip particle discrimination capabilities allowing performing real-time event-driven readout of high transverse...
A detector, equipped with 50 µm thin CMOS Pixel Sensors (CPS), is being designed for the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. MIMOSIS is being developed at IPHC aiming to meet the requirements of the MVD. The sensor is derived from the ALPIDE pixel array read-out architecture (ITS, MFT). The required radiation tolerance is significantly higher, and the required data...
We present designs and test results of a radiation-tolerant VCSEL array driver ASIC (VLAD14) fabricated in 65 nm CMOS technology. VLAD14 is a 4 × 14-Gbps driver with two designs implemented in four channels, delivers 2 mA bias and 5 mA modulation currents at 44 mW/ch and 52 mW/ch, respectively. Two designs have respective innovative structures at the output stage for high-speed and low-power...
Development of GEM detectors showed the need of a custom readout to fully exploit the advantages of this technology. GEM detectors can be realized with various shapes, also irregular, and high number of channels. GEMINI has been specifically designed to work with Triple-GEM detectors and it integrates 16 channels to perform readout with both analog and digital signal with Time over Threshold....
PACIFIC is a 64 channel mixed-signal ASIC designed for the scintillating fiber (SciFi) tracker developed for the LHCb upgrade in 2019/20. It connects without interface to the 128 channel double die SiPM arrays sensing the fibers. The analog processing begins with a current conveyor followed by a tunable fast shaper and a gated integrator. The signal is digitized with a 2bit nonlinear flash ADC...
We present a 10-Gbps 4-channel VCSEL driver with an on-chip charge pump which automatically increases the power supply voltage to ensure enough voltage headroom to the VCSEL diode operating in radiation and low-temperature environment. The charge pump efficiency is above 75%. An automatic control circuit is implemented to adjust the power supply voltage to the VCSEL. The rest of the design...
The design and measurement results of two rad-hard, ultra-low power 10-bit SAR ADCs, fabricated in two CMOS 130 nm technologies, are presented. Both prototypes are fully functional achieving, in process A excellent linearity (INL, DNL < 0.3 LSB) and ENOB above 9.5 for sampling rate up to 50 MSps, and in process B a very good linearity (INL, DNL around 0.5 LSB) and ENOB around 9.2 with sampling...
For the high granularity end-cap calorimeter upgrade (HGCAL) of CMS, HGCROC-V1 was submitted in July 2017. It has 32 channels with the low noise preamplifier followed by 25 ns shapers, ADC and TDCs for the charge and time measurements. A 512 deep memory stores the digitized data until the readout is performed at 320 Mb/s. A trigger path, done by summing clusters of 4 adjacent channels, gives a...
In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called GEMROC2. Primary application of this ASIC is readout of 10×10 cm2 3-stage GEM detector, however, it can be used for readout of other types of Micro Pattern Gas Detectors.
The ASIC has been designed in 350 nm CMOS process. Its basic functionality and parameters have been evaluated using internal...
The Silicon-Strip readout ASIC (SSA) for the pixel-strip module of the Phase II upgrades of the CMS Outer Tracker detector has been prototyped in a 65nm CMOS technology employing radiation tolerant design techniques. The SSA provides real-time primitives for the on-detector particle momentum discrimination and for the readout of the complete triggered events. This contribution will present the...
The design and measurement results of a prototype readout ASIC for the luminosity calorimeter at future linear collider are presented. The proof-of-concept ASIC, comprising 8 channels with a variable gain front-end, a differential shaper and a 10-bit SAR ADC in each channel, was fabricated in CMOS 130~nm technology. The prototype is fully functional, achieving good linearity in a wide input...
This work presents a novel method for solving the negative effects of charge sharing phenomenon. In contrary to the existing solutions, where the hit position is determined through additional analog signal processing, the presented approach is based on a digital algorithm, called COGITO, which finds the center of gravity of a group of pixels that received and processed fractional charges...
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme requirements, such as: 50x50 µm pixels, high rate (3 GHz/cm$^2$), unprecedented radiation levels (1 Grad), high readout speed, serial powering. As a consequence a new readout chip is required.
In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator designed in 65 nm CMOS...
A major upgrade for the ATLAS Inner Tracker at the Large Hadron Collider (LHC) is scheduled in 2026. The depleted CMOS pixel sensors on high resistivity substrates in LFoundry 150 nm technology have been proven to be promising for this upgrade. Recently two large demonstrators, one based on hybrid concept called LF-CPIX and the other based on monolithic concept called LF-MONOPIX have been...
The upgrade of the ATLAS tracking detector for the HL-LHC requires radiation hard silicon sensor technologies. For the development of depleted CMOS sensor for ATLAS we combined small electrodes with minimal capacitance and advanced processing to achieve radiation hard CMOS for the ITK. We developed and tested a first full-size depleted CMOS sensor based on a 180nm imaging process. The...
We report the design, implementation, and measurement results of a 2.56 GHz PLL (COLDATA PLL) and a 1.28 Gbps 10:1 serializer (COLDATA SER) IC in a 65 nm CMOS process as part of the COLDATA prototype IC for the Deep Underground Neutrino Experiment (DUNE). The PLL employs a trip-path architecture with a temperature compensated path to achieve small VCO frequency drift, stable bandwidth and low...
