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HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition

Sep 19, 2018, 11:35 AM
CAR 1.09 (aula)

CAR 1.09 (aula)

Oral Trigger Trigger


Javier Mauricio Duarte (Fermi National Accelerator Lab. (US))


Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML for boosted-jet tagging with deep networks at the LHC. We map out resource usage and latency versus network architectures, to identify the typical problem complexity that HLS4ML could deal with. We discuss possible applications in current and future HEP experiments.


Tool for Deep Neural Networks deployment on FPGA, for trigger and DAQ in HEP experiments.

Primary authors

Jennifer Ngadiuba (CERN) Javier Mauricio Duarte (Fermi National Accelerator Lab. (US)) Philip Coleman Harris (Massachusetts Inst. of Technology (US)) Nhan Viet Tran (Fermi National Accelerator Lab. (US)) Ben Kreis (Fermi National Accelerator Lab. (US)) Sergo Jindariani (Fermi National Accelerator Lab. (US)) Maurizio Pierini (CERN) Zhenbin Wu (University of Illinois at Chicago (US)) Edward Kreinard (HawkEye360) Prof. Song Han (Massachusetts Institute of Technology)

Presentation materials