21-25 July 2019
Connecticut Convention Center, Level 6
US/Eastern timezone

M4Or1B-03 [Invited]: High Throughput and Variable Temperature Test and Evaluation of Superconductor Integrated Circuits using Integrated Cryogenic Electronics Testbed

25 Jul 2019, 10:30
30m
Level 6, Room 14 ()

Level 6, Room 14

Invited Oral Presentation M4Or1B - Microelectronics II

Speaker

Mr Anubhav Sahu (HYPRES)

Description

As superconductor digital integrated circuits (ICs) mature to productization, they require rapid evaluation of multiple copies to obtain statistical operational data. These data are used for assessing model-to-hardware correlation and facilitate iterative IC design development. The Integrated Cryogenic Electronics Testbed (ICE-T) is a cryogen-free test platform, which can test multiple chips simultaneously with similar convenience to a liquid-helium immersion probe and cool-down times of between 3.3 to 4.5 hours. We have developed a three-chip insert to increase the volume of chip testing which allows simultaneous cooling of six chips with two such inserts. We report the results of test statistics collected from 27 chips across a single wafer. We have also used the ICE-T’s temperature control system to evaluate chips in the 3.5 - 6 K range. Such evaluation determines the robustness of circuit design and its tolerance to critical current fluctuations due to fabrication variation.

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