How to do ultrafast Deep Neural Network inference on FPGAs

Name: How to do ultrafast Deep Neural Network inference on FPGAs
Start: 2019-02-06T08:30:00+01:00
End: 2019-02-06T18:00:00+01:00
Location: University of Zurich, Campus Irchel

6 February 2019

University of Zurich, Campus Irchel

Europe/Zurich timezone

Overview
Timetable
Contribution List
Registration
Participant List
Poster
Getting there
Connecting to the cloud

Thea Årrestad

thea.aarrestad@cern.ch
+41 44 635 61 03

Contribution List

6. Registration

06/02/2019, 08:30

5. Welcome

Thea Aarrestad (Universitaet Zuerich (CH))

06/02/2019, 09:00

1. What is HLS4ML?

Jennifer Ngadiuba (CERN)

06/02/2019, 09:15

An introduction to the HLS4ML framework

4. Firmware implementation with SDAccel

06/02/2019, 11:00

Export HLS design to firmware with Xilinx SDAccel on Amazon cloud.

2. Optimize FPGA design: quantization and parallelization with HLS4ML

Jennifer Ngadiuba (CERN)

06/02/2019, 13:30

7. Optimize FPGA design: model compression

06/02/2019, 14:30

3. Model acceleration on cloud FPGAs

Jennifer Ngadiuba (CERN)

06/02/2019, 16:00

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How to do ultrafast Deep Neural Network inference on FPGAs

Thea Årrestad

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