CERN
Author in the following contributions
- CHIPS: CERN-HEP IC design Platform and Services
- Welcome
- Low-power SEE hardening techniques and error rate evaluation in 65nm readout ASICs
- Study of a triggered, full event zero-suppressed front-end readout chain operating up to 1 MHz trigger rate and 300 pile-up for CMS Outer Tracker upgrade at HL-LHC
