Our R&D activity is focused on the development of a new detector for the upgrade of the ATLAS pixel system at SLHC, employing thin pixel sensors together with a novel vertical integration technology offered by the Fraunhofer Institute IZM in Munich. It consists of the Solid-Liquid-InterDiffusion (SLID) interconnection, which is an alternative to the standard bump-bonding, and Inter Chip Vias (ICV) for routing the signal vertically through the readout chips. The SLID interconnection is characterized by a very thin eutectic Cu-Sn alloy, achieved through the deposition of 5 microns of Cu on both sides, and 3 microns of Sn on one side only.
The W-filled ICVs are prepared by etching through all the dielectric layers and the silicon bulk, that must be thinned down to around 50 microns. The signal transport to the readout pads on the backside of the chips allows for four side buttable devices without the presently used cantilevers for wire bonding.
We will present the status of a demonstrator module production for the ATLAS pixel system that should serve as a proof of principle for the three basic components of the R&D activity: thin planar pixel sensors (75 and 150 micron thickness) produced by the Semiconductor Laboratory of the Max-Planck Institutes in conjunction with the SLID interconnection and ICVs. The new thin pixels are connected by the SLID process to the FE-I3 chips. The SLID interconnection is obtained in the “chip to wafer” approach. This offers the possibility of singularizing the chips thus helping to increase the process yield. On the other hand it introduces a placement uncertainty due to the chip positioning on the handle wafer needed to support the ASICs during the SLID interconnection.
We will also present the results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters as the pixel size and pitch, and the planarity of the underlying layers . The test-structures were used to explore both the “wafer-to-wafer” and the “chip-to-wafer” techniques.