Sep 20 – 24, 2010
Aachen, Germany
Europe/Zurich timezone

Low-cost bump bonding activities at CERN

Sep 22, 2010, 3:05 PM
25m
Aula

Aula

Oral Packaging and interconnects Packaging and Interconnects

Speaker

Mr Sami Vaehaenen (CERN)

Description

Conventional bumping processes use electroplating for under bump metallization (UBM) and solder deposition. This process is laborious, involves time consuming photolithography, can only be performed using whole wafers and is therefore expensive in low volumes. In the low-cost development work, electroless deposition of UBM and novel solder ball placement techniques are studied as substitutes to the electroplating process in certain bump size and pitch window. Preliminary results on test and CMOS chips have shown that electroless deposited UBM’s have prospects to be used as a cost-efficient technology in future detector constructions.

Summary

Bump bonding constitutes a significant cost driver for the pixel detectors at LHC. In case of ATLAS [1] and ALICE [2] detector constructions, bump bonding was ranked as the most expensive part. The high price of fine-pitch bump bonding is due to the use of non-commercial packaging processes and is also linked to low production volumes in the HEP community. Present day costs of bump bonding would prohibit the development of larger area silicon pixel trackers in the high-luminosity upgrades of the sLHC. To overcome the problem, a small project has been established to investigate cheaper bump bonding processes.

The conventional bump bonding processes used for LHC use electroplating for under bump metallization (UBM) and solder deposition. This process is laborious and very expensive in small volumes. The detector volumes needed by HEP community are not large enough on an annual basis to enable electroplating processes at low cost. In the past electroless technology was quickly adopted by the electronics industry without careful characterization. This led to failures and reliability issues and to the poor reputation of electroless technology. However, things have changed recently and nowadays there is fully automated process equipment for precise online controlling of the plating chemistry providing reproducible depositions and increased reliability. Electroless technology is studied as a key technology in low-cost bumping project because it enables various assembly scenarios with or without solder. Electroless deposition is especially interesting because it can be used as a maskless technology and it is also high-volume capable technique.

Electroless grown UBM combined with solder ball placement offers clear cost-saving compared to electroplating processes. The penalty is generally larger bump sizes and pitches, but there are many detector applications which do not require the smallest bump size and pitch. Novel solder ball deposition techniques use preformed solder spheres which have very small dimensional tolerances. This is beneficial to avoid having a non-uniform solder volume distribution across large wafers (200 mm – 300 mm). In addition, solder balls can be reworked right after the deposition; missing solder bumps can be re-deposited and shorted bump pairs removed and individual solder balls replaced. This leads close to 100% bumping yield which is controllable.
In the low-cost development work a test chip was designed with 14.2 x 17.7 mm2 area. Each chip has about 21 000 solder bumps divided into 32 separate daisy chains. Daisy chains have been used for gathering statistical information about the bumping yields and also reliability. In addition to daisy chains Kelvin bump structures have been designed on each chip to characterize the contact resistances of different bump bonding techniques.

In the design of experiments traditional electroplated eutectic solder bump flip chip is used as a reference technique because it has shown to work very well and have had high bump bonding yields. Bump bonding using electroless UBM pads or anisotropic conductive films (ACF) have been compared to the reference technique. Daisy chain yields and contact resistances have been measured for each of the flip chip technique. Although the interconnect work is still in unfinished state the present results are summarized in the presentation.

[1] D. Muenstermann, ATLAS upgrade week, 25-Feb-2009, CERN. [http://indico.cern.ch/getFile.py/access?contribId=1&resId=0&materialId=slides&confId=52298]
[2] A. Kluge, TWEPP-2008 conference. [http://indico.cern.ch/contributionDisplay.py?contribId=131&confId=21985]

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