TWEPP 2010 Topical Workshop on Electronics for Particle Physics

Session

ASICs

15

21 Sept 2010, 09:50

Aachen, Germany

Conveners

ASICs: Parallel Session A1

• Luciano Musa (CERN)

ASICs: Parallel Session A1

• Luciano Musa (CERN)

ASICs: Parallel Session A2

• Ken Wyllie (CERN)

ASICs: Parallel Session A2

• Ken Wyllie (CERN)

ASICs: Parallel Session A3

• Luciano Musa (CERN)

ASICs: Parallel Session A3

• Luciano Musa (CERN)

16. Wideband (8 GHz GBW) pulse amplifier for the integrated camera of the Cherenkov Telescope Array

Dr David Gascon (Universitat de Barcelona (ICC-UB))

21/09/2010, 09:50

ASICs

Oral

A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC performing the digitization at 1-3 GS/s with a dynamic range of 16 bits. Input amplifiers have a voltage gain up to 20 and a bandwidth of 400 MHz. Being impossible to design an 8 GHz GBW fully differential operational amplifier in a 0.35 um CMOS...

23. Design and Assessment of a Robust Voltage Amplifier with 2.5 GHz GBW and >100 kGy Total Dose Tolerance

Mr Jens Verbeeck (K.U. LEUVEN)

21/09/2010, 10:15

ASICs

Oral

In this work a voltage amplifier with a gain-bandwidth (GBW) product of 2.5Ghz utilizing adaptive biasing has been designed, using a standard CMOS technology. The amplifier was tested under gamma-radiation and temperature and features a gain degradation of 4,5 % up to a total dose of 100kGy and 5.6 % within a temperature range of -40 till 130°C. Finally the importance of including the...

62. Developments on SPIROC family chips (SiPM Integrated Read-Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

Mr Ludovic Raux (Laboratoire de l'Accélérateur Linéaire (Orsay) / OMEGA)

21/09/2010, 11:00

ASICs

Oral

SPIROC embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge...

73. Readout Electronics for Low Dark Count Geiger Mode Avalanche Photodiodes Fabricated in Conventional HV-CMOS Technologies for Future Linear Colliders

Mrs Eva Vilella (University of Barcelona)

21/09/2010, 11:25

ASICs

Oral

The high sensitivity and excellent timing accuracy of Geiger-mode Avalanche PhotoDiodes makes them ideal sensors for particle tracking pixel detectors in high energy physics experiments. However, it is well known that they suffer from dark counts which in practice enlarge the necessary area of the readout electronics. Dark count can be dramatically reduced lowering the bias overvoltage of the...

117. Front end electronics for silicon strip detectors in 90nm CMOS technology; advantages and challenges

Mr Jan Kaplon (CERN)

21/09/2010, 11:50

ASICs

Oral

We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. A primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors on Super LHC experiments. On the example of presented design we will show critical aspects of the front...

128. A Front-end ASIC for the readout of the PMT in the KM3NeT Detector.

Mr Deepak Gajanana (NIKHEF)

21/09/2010, 12:15

ASICs

Oral

A number of possible techniques exists for detecting high energy neutrinos from space. The most widely exploited method is the detection of neutrinos in large volumes of water or ice, using the Cherenkov light from the muons and hadrons produced by neutrino interactions with matter around the detector. A photon sensor (photo multiplier tube aka PMT) is housed in a glass sphere (aka Optical...

26. A 25 GS/s sampling ASIC in a 130nm CMOS technology.

Mr Jean-Francois C. GENAT (University of Chicago)

21/09/2010, 12:40

ASICs

Oral

In the scope of time of flight measurements at the scale of a few pico-seconds, a CMOS fast sampler chip is being developed in a 130nm CMOS technology. It includes a 10-20GS/s timing generator comprising a Delay Locked Loop and programmable sampling windows, and four channels of 256 sampling cells able to record up to of 25 ns of analog information. An input discriminator triggers the freezing...

41. A Silicon Pixel Readout ASIC with 100 ps time resolution for the NA62 Experiment

Mr Giovanni Mazza (INFN sez. di Torino)

21/09/2010, 15:05

ASICs

Oral

The silicon tracker of the NA62 experiment requires the measurement of the particles arrival time with a resolution better than 200 ps rms and a spatial resolution of 300 um. A time measurement technique based on a Time to Amplitude Converter has been implemented in an ASIC in order to prove the possibility of integrate a TDC with resolution better than 200 ps in a pixel cell. Time walk...

57. GOSSIPO-3: Measurements on the Prototype of a Read-Out Pixel Chip for Micro-Pattern Gas Detectors

Dr Andre Konrad Kruth (Physics Department, University of Bonn)

21/09/2010, 15:30

ASICs

Oral

GOSSIPO-3 is the demonstrator of a front-end chip for the read-out of Micro Pattern Gas Detectors designed in IBM 130 nm CMOS in collaboration of Nikhef and the Physics Department Bonn. The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter, Low Drop Out voltage regulators for supply voltage control of the TDC, biasing circuits and...

70. A 3D vertically integrated deep n-well CMOS MAPS for the SuperB Layer0

Dr Gianluca Traversi (University of Bergamo and INFN Pavia)

21/09/2010, 15:55

ASICs

Oral

This work is concerned with the design of analog circuits for processing the signals from deep n-well (DNW) monolithic CMOS sensors. The DNW MAPS approach takes advantage of the properties of triple well structures to lay out a sensor with relatively large area (as compared to standard MAPS) read out by a classical processing chain for capacitive detectors. Recently, a very promising approach...

75. Characterisation Of The NA62 GigaTracker End Of Column Readout ASIC

Dr Matthew Noy (CERN)

21/09/2010, 16:45

ASICs

Oral

The architecture and characterisation of the End Of Column readout chip for the NA62 GigaTracker hybrid pixel detector will be presented.This chip must perform time stamping to 100 ps (RMS) or better, provide 300 µm pitch position information and operate with a dead time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other...

105. The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgrades

Tomasz Hemperek (Physikalisches Institut - Universität Bonn)

21/09/2010, 17:10

ASICs

Oral

This article elaborates on a novel pixel readout system-on-chip (SoC) that has been designed to meet the ever increasing demands of the present and future generation of LHC pixel detectors. The FE-I4 architecture has higher luminosity and rate capability as well as a smaller single pixel area compared to its predecessors and is currently the most complex chip designed for particle physics...

132. ULTIMATE: a High Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade

Dr Christine HU-GUO (DRS-IPHC (IReS), University of Strasbourg, CNRS-IN2P3)

21/09/2010, 17:35

ASICs

Oral

A pixel detector, composed of two layers of high resolution Monolithic Active Pixel Sensors (MAPS), is being designed for the STAR Heavy Flavor Tracker (HFT) upgrade. It allows topological identification of D mesons in heavy ion collisions at RHIC. The sensor chip: named ULTIMATE, is optimized for the ultimate phase of the upgrade in terms of resolution, power consumption and radiation...

5. Radiation-hard ASICS for optical data transmission in the first phase of the LHC upgrade

Prof. K.K. Gan (The Ohio State University)

22/09/2010, 09:50

ASICs

Oral

The LHC at CERN will be upgraded in two phases to increase the design luminosity by a factor of ten. The ATLAS experiment plans to add a new pixel layer to the current pixel detector during the first phase of the upgrade. The optical data transmission will also be upgraded to handle the high data transmission speed. A new driver and receiver ASIC has been designed for this new generation of...

65. Signal processing for High Granularity Calorimeter: amplification, filtering, memorization and digitalization

Laurent Royer (Lab. de Physique Corpusculaire (LPC)-IN2P3-Pole Michrau)

22/09/2010, 10:15

ASICs

Oral

A very-front-end chip dedicated to high granularity calorimeters has been designed and its performance measured. This electronics is composed of a low-noise Charge Sensitive Amplifier followed by a bandpass filter based on a gated integrator. This shaper performs intrinsically the analog memorization of the signal before its delayed digital conversion. The analog-to-digital conversion is...

98. A 256 channel 8 bit current digitizer ASIC for the Belle-II PXD

Mr Jochen Knopf (Heidelberg University)

22/09/2010, 11:00

ASICs

Oral

The international DEPFET collaboration is developing a low mass vertex detector (PXD)for the future BELLE-II experiment at the SuperKEKB particle accelerator in Japan. The PXD is based on monolithic arrays of DEPFETs which are read out in a rolling shutter mode. The Drain Current Digitizer ASIC (DCD-B) is used for reading out this detector matrix. It provides 256 channels of Analog-Digital...

100. The GBT-Serdes ASIC prototype: test features and preliminary results

Mr PAULO MOREIRA (CERN)

22/09/2010, 11:25

ASICs

Oral

In the framework of the GigaBit Transceiver project (GBT), a prototype of the GBT-SERDES ASIC has been developed. In charge of the serialization-deserialization of the data, including Reed-Solomon encoding, clock recovery, precise PLLs and complex frame-alignment procedure, this chip has been designed in a commercial 130nm CMOS technology to sustain high radiation doses and operate at 4.8...

106. The Design for Test Architecture in Digital Section of the ATLAS FE-I4 Chip

Dr Vladimir Zivkovic (NIKHEF Institute)

22/09/2010, 11:50

ASICs

Oral

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used during the experiment, the so-called production test to detect faulty devices after the manufacturing has to be...

115. A 16:1 Serializer ASIC for Data Transmission at 5 Gbps

Datao Gong (Southern Methodist Univeristy)

22/09/2010, 12:15

ASICs

Oral

A high speed, low power 16:1 serializer is developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. It operates from 4.0 to 5.8 Gbps in the lab test. Its total jitter is measured to be 62 ps and the bathtub scan demonstrates a 122 ps opening at BER of less than 10-12 level at 5 Gbps. The measured power consumption is 507 mW at this data rate. A proton test of this chip is...

148. Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

Mr Michal Bochenek (CERN)

22/09/2010, 12:40

ASICs

Oral

We present designs and hopefully the first test results of two DC-DC switched capacitor converters developed in 0.13μm technology. Both circuits will be used as the building blocks in the power distribution system proposed for the upgraded ATLAS Inner Detector.