Speakers
Description
This contribution will present the status and latest results of the CMOS work package within the CERN-RD50 collaboration. This will consist of describing the RD50 Data AcQuisition System (DAQ) for the test chip RD50-MPW1 and the obtained results, including chip hit maps and pixel address decoding debugging. Measurements of the effects of the clock rate of the on-chip state machine on the on-chip pixel address line crosstalk will also be shown. Post-layout simulations to study possible crosstalk between on-chip pixel address lines and efforts to reduce these effects in a future prototype will be presented as well.
An update on the manufacture of the test chip RD50-MPW2 and its expected delivery date will be presented, along with a description of the resources available and in development for the evaluation of this chip. This will include a brief description of the status of the chip board, FPGA firmware and readout system architecture.
S. Powell, E. Vilella, O. Alonso, M. Barbero, R. Casanova, G. Casse, A. Dieguez, M. Franks, S. Grinstein, J. M. Hinojo, E. Lopez, R. Marco-Hernandez, N. Massari, F. Munoz, R. Palomo, P. Pangaud,. Vossebeld, C. Zhang