PRR of the NSW Trigger Processor Part 2

Name: PRR of the NSW Trigger Processor Part 2
Start: 2020-05-06T14:00:00+02:00
End: 2020-05-06T18:25:00+02:00
Location: CERN

Wednesday 6 May 2020, 14:00 → 18:25 Europe/Zurich

Vidyo Only (CERN)

Vidyo Only

CERN

Description

Reviewers

Hucheng Chen (BNL)
Stefan Haas (CERN)
Junpei Maeda (Kobe)
Tomoyuki Saito (Tokyo)
Shaochun Tang (BNL)

Ex-officio

Martin Aleksa (CERN)
Didier Ferrere (Geneva)
Francesco Lanni (BNL)
Lorne Levinson (Weizmann)
Ludo Pontecorvo (CERN)
Stefano Veneziano (Roma)
Stephanie Zimmermann (Freiburg)

- 14:00 → 14:05
  
  Review procedure 5m
  
  Speaker: Hucheng Chen (Brookhaven National Laboratory (US))
- 14:10 → 14:20
  
  Introduction & Review Scope 10m
  
  Speaker: Stephanie Ulrike Zimmermann (Albert Ludwigs Universitaet Freiburg (DE))
  
  NSW_TP_hardware_PRR2_20200506.pdf
  
  NSW_TP_hardware_PRR2_20200506.pptx
  
  Response to the NSW Trigger Processor PRR report.docx
  
  Response to the NSW Trigger Processor PRR report.pdf
- 14:20 → 16:20
  Trigger Processor Firmware
  
  including corresponding validation/tests using carrier v2/mezzanine v2
  
  Firmware Requirements & implementation V2.1
  
  NSWTP_FW_Requirements_Implementation_V2.0.pdf
  - 14:25
    
    Micromegas: L1A and readout (thru carrier). Algorithms and time alignment. 20m
    
    Speakers: Nathan Felt (Harvard University (US)), Nathan Felt (Unknown), Thiago Costa De Paiva (University of Massachusetts (US))
    
    mML1aReadoutAlgorithmsTimeAlignment (3).pdf
  - 14:55
    
    sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment 15m
    
    Speakers: Enrique Kajomovitz Must (Department of Physics), Enrique Kajomovitz Must (Technion, Israel Institute of Technology)
    
    sTGC_ Stage 0 and L1A readout.pdf
  - 15:25
    
    Merge block, and output formatter to SL. 20m
    
    Speaker: George Chatzianastasiou (University of Innsbruck (AT))
    
    sTGC_TP_Merge_06.05.2020_final.pdf
    
    sTGC_TP_Merge_06.05.2020_final.pptx
  - 15:55
    
    Results of combined tests with SL. Fixed latency. Latency measurements. 15m
    
    Speaker: Lorne Levinson (Weizmann Institute of Science (IL))
    
    PRR_testsWithSectorLogic.pdf
    
    PRR_testsWithSectorLogic.pptx
- 16:20 → 16:35
  
  Coffee break and rest from staring on a screen 15m
- 16:35 → 16:55
  
  Carrier v3 design.Validation/test results (Bucarest/Samway, standalone) 20m
  
  Speakers: Andrei Scurtu (Samway SRL), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)
  
  Schematics, assembly files
  
  TP_V3_validation_PP2_AS_v3.pdf
- 17:00 → 17:20
  
  Board test protocol and procedures (for series production); acceptance criteria 20m
  
  Speakers: Ricardo Di Curzio Lera (University of Massachusetts (US)), Thiago Costa De Paiva (University of Massachusetts (US))
  
  HW acceptance tests
  
  NSWTP_HWAcceptanceTests.pdf
  
  TCPaiva_NSWTP_PRR_AT_20200506.pdf
- 17:30 → 17:50
  
  Production plan and schedule 20m
  
  Speakers: Mihai Savu (Samway Electronic), Sorin Martoiu (Horia Hulubei National Institute of Physics and Nuclear Enginee)
  
  Production Planning_v2.pdf
- 18:05 → 18:25
  
  Installation plans @ P1 and commissioning 20m
  
  Speaker: Alexander Naip Tuna (Harvard University (US))
  
  Tuna-2020-05-06-nswtriggerP1.pdf