Speaker
Description
Authors:
Ikuo Kurachi, Toru Tsuboyama, Makoto Motoyoshi, Miho Yamada, Kazuhiko Hara, Yasuo Arai
Smart and unique three-dimensional (3D) chip stacking process is proposed for detectors using high energy physics experiments. In this process, chip-on-chip scheme with base chips fabricated by silicon-on-insulator (SOI) technology is considered instead of wafer-on-wafer or chip-on-wafer schemes because of process feasibility even for shuttle run die. Unique 3 um Au micro bump formation called as Au cylinder bump has developed and newly introduced to connect electrically between the chips with less planarization process of the chips. Low via resistance of around 0.35 Ω/via was obtained. Submicron through buried oxide via (TBV) which is fabricated in wafer processing of SOI chips are used as via between the upper chip and bonding pads to etch off handle wafer silicon of the upper chip instead of generally used through silicon via (TSV). The detector was fabricated by using this 3D process in pixel. The beta-lay tracking from 90Sr was successfully observed. More than 99% via yield was also confirmed.
