MiniCactus : a HV-CMOS monolithic timing sensor with sub 100 ps resolution

21 Sept 2022, 11:20
20m
Terminus Hall

Terminus Hall

Oral ASIC ASIC

Speaker

Fabrice Guilloux (Université Paris-Saclay (FR))

Description

MiniCACTUS is a monolithic CMOS sensor designed for tagging Minimum Ionizing Particles at the 100 ps level. The sensor features an array of diodes, without internal amplification, of surface 1.0 mm² and 0.5 mm², with an analog front-end and discriminator per pixel. A time resolution of 88 ps has been measured on a 0.5 mm² pixel from a 200 µm-thick sensor tested at CERN. 300 micron and 200 micron sensors with optimized FE parameters and increased bias voltage will be tested May-July 2022. Significant improvements on the timing resolution, already checked in lab, are expected.

Summary (500 words)

I. Introduction
A monolithic timing detector, intended for future high energy experiments, is currently being developed on the LF 150 nm HV-CMOS process. The radiation hardness of this technology has already been demonstrated with tracking detectors developed for ATLAS Inner Tracker upgrades.
A first large size (1 cm²) demonstrator has been designed, fabricated and tested with this process. The results of this first prototype were promising in terms of breakdown voltage, charge collection uniformity over large diodes, production yield, but an unexpected low S/N observed during tests prevented precise timing studies. This low S/N issue was attributed to the increase of the detector capacitance due to large power rails crossing the pixels. This issue has been adresses with a new smaller size prototype (2.5 mm x 3.5 mm), called MiniCACTUS.

II. Sensor Description
The main architecture difference between the MiniCACTUS and the CACTUS is the implementation of the front-end electronics for each pixel at the column level, avoiding large power rails in the active area. The front-end electronics comprises an AC-coupled charge sensitive amplifier, a discriminator and a 4-bit DAC for threshold tuning. One pixel (among 8) has its AC coupling capacitance integrated on top of the diode. Other pixels are mostly passive. All DACs of the chip are programmable through a slow control block. The baseline pixel pitches are 1 mm  1 mm and 0.5 mm  1 mm. Two additional smaller pixels (50 µm  50 µm and 50 µm  150 µm) are implemented as test structures.
Standard HR wafers have been thinned (100 µm and 200 µm) and post processed for backside polarization. Substrates can be safely biased to at least -300V. All pixels have been calibrated with 55Fe and 241Am sources.
III. Test-beam results
A testbeam campaign has been performed at SPS (CERN, H4 beamline) during a RD51 testbeam period in October 2021 with 200 GeV/c muons and pions. Sensors with 200 µm and 100 µm thickness have been tested A MCP with time resolution better than 20 ps has been used as timing reference. Data was acquired at 10 Gs/s with a LeCroy WaveRunner 8254 scope. The best timing results have been obtained for the pixel 8 from the 200 µm thick sensor. The MPV obtained with MIPs is 137.5 mV for this pixel. The preliminary measured timing resolution for this pixel with nominal FE settings at −280 V bias voltage is 88 ps, after time walk effect corrections.

Sytematic in-lab measurements have been done in order to understand and improve the parameters limiting the timing resolution. According to these tests, optimizing the FE parameters and increasing the bias voltage of the diode improve the timing resolution. Since the results with the 200 µm sensor are better than with the 100 µm sensor, we expect also an improvement with a thicker sensor (300 µm) thanks to larger signal expected. All these conclusions and hypotheses will be checked and confirmed during testbeam campaigns planned in May and July 2022 at CERN.

Authors

Fabrice Guilloux (Université Paris-Saclay (FR)) Prof. Philippe Schwemling (Université Paris-Saclay (FR)) Jean-Pierre Meyer Tomasz Hemperek (University of Bonn (DE)) Yavuz Degerli (Université Paris-Saclay (FR))

Presentation materials