TWEPP 2022 Topical Workshop on Electronics for Particle Physics

19 Sept 2022, 09:00 → 23 Sept 2022, 17:00 Europe/Zurich

Alex Kluge (CERN), Johan Alme (University of Bergen (NO))

The workshop covers all aspects of electronic systems, components and instrumentation for particle and astro-particle physics experiments such as: electronics for particle detection, triggering, data-acquisition systems, accelerator and beam instrumentation.
Operational experience of electronic systems and R&D in electronics for LHC, High Luminosity LHC, FAIR, neutrino facilities and other present or future accelerator projects are the major focus of the workshop.

The purpose of the workshop is:
- Present original concepts and results of research and development for electronics relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities;
- Review the status of electronics for running experiments and accelerators;
- Identify and encourage common efforts for the development of electronics;
- Promote information exchange and collaboration in the relevant engineering and physics communities.

The main topics of the workshop will be recent research and developments in the following areas:
- Highly integrated detectors and electronics;
- Custom Analogue and Digital Circuits;
- Programmable Digital Logic Applications;
- Optoelectronic Data Transfer and Control;
- Packaging and Interconnect Technologies;
- Radiation and Magnetic Field Tolerant Systems;
- Testing and Reliability;
- Power Management and Conversion;
- Grounding and Shielding;
- Design Tools and Methods.

The workshop programme will include invited plenary talks, sessions for oral presentations and poster presentations.

Agenda overview:

Sept 19, 2022, 9:00-14:00, Registration

Sept 19, 2022, 14:00-18:00, Plenary presentations (organised by the local organising committee)

Sept 19, 2022, evening, Welcome reception in conference hotel

Sept 20 - 22, 9:00-18:00 and Sept 23, 9:00-12:30 scientific program in plenary, parallel and poster sessions

Sept 20, 2022, evening, social activity

Sept 21, evening, conference dinner

Sept 23, 2022, 14:00-17:00, tutorial: high speed PCB design (https://indico.cern.ch/event/1127562/page/25065-training-tutorial, registration required)

Information about registration to the workshop and local organisation is available on: https://twepp2022.w.uib.no/

Authors are invited to submit abstracts and summaries describing original developments and new contributions, including recent progress, in the workshop topic areas.

Abstracts (max. 100 words long) and summaries (max. 500 words long) along an optional file containing diagrams or plots must be submitted through the Integrated Digital Conference tool at https://indico.cern.ch/e/twepp2022.

The summary will be the basis for paper selection. The summary should describe quantitative specifications of the work, challenges,  implementation and results.

Submissions without comprehensive summary will not be considered. Submissions directly from the presenters are encouraged. Summaries should clearly describe the aspects of the work relevant to the topics of TWEPP.  Standard summaries targeted to physics or detector instrumentation conferences might need to be updated accordingly.

The submission deadline is April 30, 2022. From this year on, no extensions are foreseen.

Abstracts will be made available at the time of the workshop and will include all contributions selected for either oral or poster presentation.
The proceedings of the workshop will be published in a peer reviewed Journal.

Information concerning the workshop scientific programme and submissions is available at: https://indico.cern.ch/e/twepp2022 

Enquiries can be directed to the Workshop Secretariat, by email at twepp@cern.ch

Local organisation information is be available on https://twepp2022.w.uib.no/ 

Enquiries concerning the local organisation can be directed to the local organisation committee, by email at twepp2022@uib.no

Scientific organisation
A. Kluge (CERN, CH, Chair)
J. Alme (UiB, NO)
J.P. Cachemiche (CPPM–IN2P3, FR)
H. Chen (BNL, US)
W. Dabrowski (AGH, PL)
S. Danzeca (CERN, CH)
M. French (RAL, UK)
P. Gui (SMU, US)
M. Hansen (CERN, CH)
C. G. Hu (IPHC-IN2P3, FR)
G. Iles (Imperial College, UK)
C. Joram (CERN, CH)
A. Ricci (CERN, CH, Secretary)
A. Rivetti (INFN, IT)
W. Snoeys (CERN, CH)
F. Vasey (CERN, CH)
K. Wyllie (CERN, CH)

Organised by the Department of Physics and Technology, University of Bergen, with support from the Western Norway University of Applied Sciences and from the European Organization for Nuclear Research (CERN).

Monday, 19 September

09:00 → 14:00 Registration

14:00 → 15:20 Welcome

Convener: Johan Alme (University of Bergen (NO))

14:00 Introduction

Speaker: Alex Kluge (CERN)

20220919TWEPPintro.pdf

20220919TWEPPintro.pptx

14:20 Welcome

Speaker: Øyvind Frette

14:50 Norway and accelerators - a historical view

Speaker: Dieter Roehrich (University of Bergen (NO))

Norwegian_Accelerator_TWEPP_v1.pdf

Norwegian_Accelerator_TWEPP_v1.pptx

15:20 → 15:40 Coffee break

15:40 → 17:50 Welcome

Convener: Johan Alme (University of Bergen (NO))

15:40 Bringing proton computed tomography into the treatment room

Speakers: Matthias Richter (University of Oslo (NO)), Matthias Richter (DEPARTMENT OF PHYSICS AND TECHNOLOGY, UNIVERSITY OF BERGEN)

2022-09-19_MRichter_TWEPP22_pCT.pdf

16:25 How design enables discovery: a Giant Magnetar Flare observed by the Atmosphere-Space Interactions Monitor

Speaker: Martino Marisaldi

220919_TWEPP_Marisaldi_giant-magnetar-flare-ASIM.pdf

220919_TWEPP_Marisaldi_giant-magnetar-flare-ASIM.pptx

17:10 6 Mask-Based Nanometer Resolution Lithography with Atoms

Speaker: Bodil Holst

17:35 Practical information

Speaker: Johan Alme (University of Bergen (NO))

TWEPP 2022 - practical information.pdf

TWEPP 2022 - practical information.pptx

18:30 → 20:00 Welcome reception

Tuesday, 20 September

09:00 → 10:00 ASIC

Conveners: Marcus Julian French (Science and Technology Facilities Council STFC (GB)), Christine Guo Hu (Centre National de la Recherche Scientifique (FR))

09:00 HKROC: an integrated front-end ASIC to readout photomultiplier tubes for the Hyper-Kamiokande experiment

HKROC is an ASIC designed to readout the photomultiplier tubes of the Hyper-Kamiokande experiment. With a large number of channels and stringent readout requirements in terms of noise, speed and dynamic range, the ASIC is very challenging and innovative. Each HKROC channel embeds low-noise preamplifier-shapers, a 10-bit SAR-ADC for the charge measurement (up to 2500 pC) and a TDC for the Time-of-Arrival (ToA) measurement with 25 ps binning. HKROC is auto-triggered and includes all necessary ancillary services as bandgap circuit, PLL and threshold DACs. We will present the experimental results of the first HKROC prototype received in January 2022.

Speaker: Selma Conforti Di Lorenzo (OMEGA (FR))

TWEPP2022_HKROC.pdf

09:20 RD53 pixel chips for ATLAS and CMS

RD53 Collaboration is a joint effort between ATLAS and CMS that was
established in 2013, and extended in 2018, to develop readout chips
for the HL-LHC pixel detectors in 65nm technology.
Main operational constraints for the readout electronics are: the
extremely harsh radiation environment (1 Grad), high hit (3GHz/cm2)
and Trigger rates (4 MHz), high data rate readout (5 Gb/s).
This work will describe all architectural choices that have been
performed in order to cope with these extreme operating conditions.
Measurements results showing that ATLAS and CMS experiment
specifications are met will be presented.

Speaker: Roberto Beccherle (INFN, Pisa (IT))

RB_20220920.pdf

09:40 The COLUTA ADC ASIC in the ATLAS HL-LHC Liquid Argon Calorimeter Readout

The upgraded high-luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon Calorimeter readout operating at 40MHz with 16-bit dynamic range. The COLUTA is a 65nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application, coupling a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC. A Digital Data Processing Unit (DDPU) outputs sample data continuously via 640 Mbps serial LVDS. Prototype COLUTA performance above specification at >11.5 ENOB for relevant frequencies and “Slice Testboard” integration test results will be presented.

Speaker: Gabriel Pinheiro Matos (Columbia University (US))

The_COLUTA_ADC_ASIC_and_the_ATLAS_HL-LHC_Liquid_Argon_Calorimeter_Front_End_Readout.pdf

09:00 → 10:00 Power, Grounding and Shielding

Conveners: Magnus Hansen (CERN), Hucheng Chen (Brookhaven National Laboratory (US))

09:00 Silent and slim DC-DC converters for the CMS MTD BTL and ECAL Barrel for HL-LHC.

The MIP Timing Detector (MTD) is introduced in the CMS experiment to measure the production time of MIPs. Power Conversion Cards (PCCs) regulate low-voltages in the MTD barrel region. They host three radiation and magnetic field tolerant DC-DC converters. The height of the PCC is limited to 7 mm. This necessitated the development of custom inductors and shields. Additionally, the CMS Electromagnetic Calorimeter is upgraded. On-detector Low Voltage Regulator (LVR) cards host six DC-DC converters and one linear regulator. We will present for both cards their design evolution, stack-up and layout optimization, noise filtering choices, reliability and performance evaluations.

Speaker: Tomasz Gadek (ETH Zurich (CH))

certificate2022_gadek.pdf

TWEPP_2022.pdf

09:20 The powering systems of the CMS tracker for HL-LHC

The upgraded CMS tracker for HL-LHC is going to require more than 200 kW power. Two different powering strategies are being adopted for the Inner Tracker and the Outer Tracker. The talk describes the two powering schemes and discusses the intrinsic constrains. Specifications for the powering units and for the cables of the two systems are outlined in combination to preliminary results with prototypes

Speaker: Simone Paoletti (Universita e INFN, Firenze (IT))

CMS-Powering-TWEPP2022.pdf

09:40 Prototyping Serial Powering for the ATLAS ITk Pixel Detector

The high luminosity upgrade for the LHC at CERN requires a complete overhaul of the current inner detectors of ATLAS and CMS. A serial powering scheme has been chosen to cope with the constraints of the new pixel detectors. A prototype stave consisting of up to 8 quad modules, based on the new readout chips developed by the RD53 collaboration in 65 nm CMOS technology, RD53A and ITkPixV1, has been set up in Bonn. This contribution covers the results obtained with RD53A modules and presents first measurements with a full ITkPixV1.1 serial powering chain.

Speaker: Thomas Christian Senger (University of Bonn (DE))

20_09_2022_TWEPP_Thomas_Senger.pdf

10:00 → 10:30 Coffee break

10:30 → 11:15 Invited

Convener: Alex Kluge (CERN)

TWEPP-2022_UVVM.pptm

10:30 Detector design in HEP

Speaker: Werner Riegler (CERN)

TWEPP_2022_small.pdf

TWEPP_2022_small.pptx

11:20 → 12:20 ASIC

Conveners: Marcus Julian French (Science and Technology Facilities Council STFC (GB)), Christine Guo Hu (Centre National de la Recherche Scientifique (FR))

11:20 Simulated verification of the ASIC functionality and radiation tolerance for the HL-LHC ATLAS ITk Strip Detector

ASICs are important components in many HEP detectors and their functional simulation ensures successful operation while minimizing the number of long production cycles. Three radiation-tolerant ASICs (HCC, AMAC, and ABC) will perform the front-end readout, monitoring, and control of the outer layers of the ITk Strip particle tracker for the HL-LHC ATLAS detector. Simulated verification with the python-based cocotb framework allows for sophisticated tests with major contributions from students and firmware non-experts. The verification program includes interactions between multiple ASICs, realistic HL-LHC data flows, operational stress tests, and a focus on mitigation of disruptive Single Event Effects due to radiation.

Speaker: Jeff Dandoy (University of Pennsylvania (US))

ASICSimulation_TWEPP_JeffDandoy_Sep2022.pdf

11:40 Performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the strip sensor readout ASIC of the CMS Outer Tracker at the HL-LHC

This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the final version of the Short-Strip readout ASIC for the CMS Outer-Tracker PS-module. The ASIC performance is characterised at different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises Total-Ionising-Dose (TID) tests and Single-Event-Effects (SEEs). Wafer-level testing provided a large dataset to evaluate the production yield. The presented test results are in agreement with the design simulations and are well within the application requirements for operation in the CMS outer-tracker at the HL-LHC.

Speaker: Alessandro Caratelli (CERN, EPFL)

2022.09.14_SSA_ASIC.pdf

12:00 A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA Micro-Vertex Detector

The ToASt ASIC is a 64 channel integrated circuit designed for the readout
of the Silicon Strips that will equip the Micro-Vertex Detector of the PANDA
experiment.
The ASIC is synchronous to a 160 MHz clock, which defines also the
time resolution. A common time stamp is distributed to all channels to
provide a common time reference for time of arrival and time over threshold
measurements. Two 160 Mb/s serial lines provide the interface to the data
concentrator.
ToASt is implemented in a commercial 110 nm CMOS technology with triplicated
logic to protect against single event upsets.

Speaker: Giovanni Mazza (INFN sez. di Torino)

TWEPP22_ID100_GMazza.pdf

11:20 → 12:20 Trigger

Conveners: Alex Kluge (CERN), Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

11:20 Architecture and Prototype of the CMS Global Level-1 Trigger for Phase-2

We present the architecture and current state of prototype firmware of the CMS Level-1 Global Trigger, the final stage of the Level-1 trigger for Phase-2 of the operation of the LHC. Based on high-precision inputs from the muon-, calorimeter-, track- and particle flow triggers, the Global Trigger evaluates O(1000) cut-based and neural-net based algorithms in a system of up to thirteen Xilinx Ultrascale Plus based ATCA processing boards interconnected by 25 Gb/s optical links. In order to optimize usage of resources and to facilitate routing, the main algorithms, including the DSP-based calculation of invariant masses, are implemented at 480 MHz.

Speaker: Hannes Sakulin (CERN)

2022_09_20_CMSP2GT_HannesSakulin_V1-4.pdf

11:40 An ATCA Processor for Level-1 Trigger Primitive Generation and Readout of the CMS Barrel Muon Detectors

An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. Furthermore, it provides readout for the DT detector. The ATCA processor is based on a Xilinx XCVU13P FPGA, it receives data via 10 Gbps optical links and transmits track segments via 25 Gbps optical links. The processor is instrumented with a Zynq Ultrascle+ SoM connected with an SSD which provides for enhanced monitoring and control information. The design of the board as well as results on its performance are presented.

Speaker: Ioannis Bestintzanos (University of Ioannina (GR))

TWEPP_ 2022_BMTL1_Trigger_Processor_Bestintzanos.pdf

12:00 Particle Flow Reconstruction for the CMS Phase-II Level-1 Trigger

The upgrade of the CMS detector for the high-luminosity LHC will include track-finding for the first time in the Level-1 trigger, enabling Particle Flow reconstruction of every event in addition to comprehensive pileup mitigation. The Correlator trigger will reconstruct isolated leptons and photons, hadronic jets, and energy sums, assisted in many cases by machine learning to benefit from the complete particle-level event record. We present the logic of these algorithms, possible implementations using large FPGAs and their demonstration in prototype hardware, in addition to the expected physics performance.

Speaker: Christian Herwig (Fermi National Accelerator Lab. (US))

herwig_L1CT.pdf

12:30 → 14:00 Lunch

14:00 → 15:00 ASIC

Conveners: Christine Guo Hu (Centre National de la Recherche Scientifique (FR)), Marcus Julian French (Science and Technology Facilities Council STFC (GB))

14:00 Performance of ALTIROC2 readout ASIC with LGADs for ATLAS HGTD picosecond MIP timing detector

ALTIROC2 is the first full-scale 225-channel ASIC prototype designed for LGAD (low Gain Avalanche Diodes) readout, as part of the new ATLAS HGTD detector foreseen for the High Luminosity-LHC upgrade. The scientific goals require to detect charges as small as 2 fC with a 95% efficiency and to exhibit a 25 ps jitter for 10 fC input charge with less than 5 mW/channel. The 2x2 cm² chip was fabricated in CMOS 130nm in 2021 and on-going extensive characterisation results will be presented for the ASIC bump-bonded onto the LGAD detector, as well as preliminary results of TID and SEE tests.

Speakers: Maxime Morenas (OMEGA (FR)), Maxime Morenas (OMEGA)

ALTIROC2_ATLAS_HGTD.pdf

ALTIROC2_ATLAS_HGTD.pptx

certificateTwepp2022.pdf

14:20 From the first full chain precision timing prototype ETROC1 (4x4) to the first full size full functionality ETROC2 (16x16) for CMS MTD Endcap Timing Layer (ETL) upgrade

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC1 has been extensively tested, another round of beam test is now on going at Fermilab since March 2022. The performance of ETROC1 will be summarized, with emphasis on the main issue learned on the 40MHz noise after bump bonded with LGAD sensor and most recent beam test results. The ETROC2 design will be presented, to be submitted in summer 2022, including the development strategy from ETROC1 to ETROC2 and how the 40MHz noise issue is addressed.

Speaker: Tiehui Ted Liu (Fermi National Accelerator Lab. (US))

ETROC abstract and summary for TWEPP 2022.docx

ETROC-TWEPP-Sept-2022-Ted-final.pdf

14:40 Results with the TOFHIR2B revision of the front-end ASIC of the CMS MTD Barrel Timing Layer

The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD), which will consist of barrel and endcap timing layers, BTL and ETL. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs read-out by TOFHIR2 ASICs in the front-end system. A resolution of 30 ps for MIP signals is expected at the beginning of HL-LHC operation, degrading to 60 ps at the end of operation due to SiPMs radiation damage.
We present an overview of the TOFHIR2 requirements and design, and the recent results of the measurements with its final version, TOFHIR2B.

Speaker: Alessio Boletti (LIP, Lisboa (PT))

TOFHIR2-summary-TWEPP_2022_final.docx

TWEPP2022_TOFHIR_Boletti.pdf

14:00 → 15:00 Trigger

Conveners: Alex Kluge (CERN), Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

14:00 The ALICE central trigger system for LHC Run 3

The LHC interaction rate at ALICE will be increased to 50 kHz in Pb--Pb collisions and 1 MHz in pp collisions. In order to read out data at these interaction rates the ALICE Central Trigger System was upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System, based on a Passive Optical Network. The main hardware is a universal trigger board based on the Xilinx Kintex Ultrascale FPGA, which can function as a Central Trigger Processor, Local Trigger Unit and monitoring interfaces. The trigger system, its installation and commissioning will be presented.

Speaker: Marian Krivda (University of Birmingham (GB))

TWEPP_2022.pdf

14:20 Sector Logic Development for the ATLAS Level-0 Muon Trigger at HL-LHC

The design of the Sector Logic (SL) for the ATLAS Level-0 muon trigger at HL-LHC and the milestones achieved on the hardware and firmware developments are presented. The first prototype of the SL board was produced, and all the functions have been demonstrated and confirmed. Fast tracking using Thin Gap Chamber (TGC) hits, a core part of the Level-0 muon trigger, has been developed for full coverage of the endcaps and the performance was confirmed with post-synthesis simulations, demonstrating the feasibility of processing the TGC hits from ~7000 channels within ~100 ns using single XCVU13P FPGA for muon tracking.

Speaker: Yuki Mitsumori (Nagoya University (JP))

Attachment1.pdf

Attachment2.pdf

TWEPP2022_slide_mitsumori.pdf

14:40 New developments in the MDT Trigger Processor for the ATLAS Level-0 Muon Trigger at the HL-LHC

The MDT Trigger Processor (MDTTP) processes muon trigger candidates along with Monitored Drift Tubes (MDT) hits to improve the accuracy of the transverse momentum calculation at the first-level (level-0) of the muon trigger. The challenge would be processing all candidates in a bunch crossing to meet latency requirements of High-Luminosity LHC. The MDTTP hardware is based on the Apollo ATCA platform. A complete hardware demonstrator is available and an updated prototype has been recently developed. We present here the progress on hardware and firmware development along with recent performance studies from simulations.

Speaker: Kostas Ntekas (University of California Irvine (US))

MDTTP_TWEPP2022.pdf

15:00 → 15:30 Coffee break

15:30 → 16:15 Invited

Convener: Ken Wyllie (CERN)

TWEPP-2022_UVVM.pptm

15:30 Invited - Measuring charged-particles with 10ps time resolution using innovative 3D trench-type silicon pixel sensors

Measuring charged-particles with 10ps time resolution using innovative 3D trench-type silicon pixel sensors

Future collider experiments operating at very high instantaneous luminosity will greatly benefit in using detectors with excellent time resolution to facilitate event reconstruction. As an example, when the LHCb experiment will operate at 1.5x1034/cm/s after its Upgrade2, 2000 tracks from 40 proton-proton interactions will cross the vertex detector (VELO) at each bunch crossing, and to properly reconstruct primary vertices and b-hadron decay vertices VELO hit time stamping with at least 50ps accuracy will be needed. To fulfill these requirements, several technologies are under study and one of the most promising today is the 3D trench silicon pixel, developed by the INFN TimeSPOT Collaboration. These 55μmx55μm pixels are built on a 150μm-thick silicon and consist of a 40μm-long planar junction located between two continuous bias junctions, providing charge-carriers drift paths of about 20μm and signals’ total durations close to 300ps. The design of these sensors, their detailed simulation, their characterization both in laboratory and on the beam test, and the performance of irradiated sensors will be presented in this talk, showing that 3D trench-type silicon pixels appear to be a promising technology matching the requirements of future vertex detectors operating at very high instantaneous luminosity.

Alessandro Cardini, after his Master's degree in Physics at the University of Pisa (Italy) in 1989, with a thesis on innovative vertex detectors based on scintillating microfibers bundles, got his PhD in Physics at the same University in 1993, working on the silicon strip vertex detector and correlated charm production studies at the CERN fixed-target experiment WA92. After a 3-years post-doctoral period at UCLA working on the CERN neutrino oscillation search experiment NOMAD, he became a permanent Researcher at Istituto Nazionale di Fisica Nucleare (INFN) Italy. In the first years he participated to the construction of the ATLAS barrel MDTs and then to the development and construction of the first triple-GEM detectors to be used at LHC, the LHCb triple-GEM muon system detectors. From 2012 to 2015 he was appointed LHCb Muon System Project Leader and then elected as Italian LHCb Coordinator in the period 2015-2018. Always involved in innovative detector R&Ds, Alessandro Cardini joined in 2008 the DREAM Collaboration to develop dual-readout calorimeters for future HEP applications. He has also been involved in other R&D initiatives to study cryogenic solid-state photodetectors for very low threshold energy detectors for rare-events applications. In more recent years he has been one of the proponents of the INFN R&D initiative TimeSPOT to develop new silicon pixel detectors with time resolutions in the 10ps range. In October 2022 Alessandro Cardini will start its mandate as Director of the INFN Institute in Cagliari, an Institute with a long-standing tradition in detectors and ASICs development for CERN experiments.

Speaker: Alessandro Cardini (INFN Cagliari, Italy)

TimeSPOT_TWEPP2022_Final.pdf

TimeSPOT_TWEPP2022_Final.pptx

16:20 → 16:40 ASIC

Conveners: Christine Guo Hu (Centre National de la Recherche Scientifique (FR)), Marcus Julian French (Science and Technology Facilities Council STFC (GB))

16:20 TimeSPOT ASIC developments for 4D-Tracking

We present the timing measurements performed using the Timespot1 ASIC after hybridization onto a sensor pixel matrix featuring 32x32 channels. The ASIC is fabricated in CMOS 28-nm technology and integrates 1024 readout pixels, each equipped with a fast Analog Front End and a high-resolution TDC. The sensor is a matched matrix of 1024 3D silicon sensors, having pitch of 55 µm and processed in a so-called trench geometry, highly optimized for timing. Such sensor technology has been already proven to be capable of an intrinsic timing resolution around 10-ps per hit.

Speaker: Adriano Lai (Universita e INFN, Cagliari (IT))

3D-trenchSensor.png

certificate2022_lai.pdf

Timespot1_pict.jpg

Track_layer_PCB.png

TWEPP_ASIC_ALai.pdf

16:20 → 16:40 Trigger

Conveners: Alex Kluge (CERN), Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

16:20 Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

The Global Trigger will bring even-filter-like capability to the High-Luminosity trigger system of the ATLAS experiment. Its several firmware-based nodes will run on identical hardware, the Global Common Module, an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was developed to mitigate risks of complex design and power management. GRM features a Xilinx Versal Prime system-on-chip to communicate
with the FELIX subsystem and trigger processors for readout and system control; a lpGBT chip enables emulation of the detector front-ends. This summary presents the ongoing testing of key functionalities of GRM.

Speaker: Filiberto Bonini (Brookhaven National Laboratory (US))

1.GRM_board.jpg

2022.09.20_TWEPP_GRMv1.1.pdf

2.GRM_block-diag_1.png

3.GRM_lpGBT_block-diag_2.png

16:40 → 17:40 Tuesday posters session

poster_locations_Tue.jpg

poster_plan_hall.jpg

poster_plan_lounge.jpg

16:40 A 64-channel waveform sampling ASIC for SIPM in space-born applications

The implementation of a 64-channel ASIC for the readout of Silicon Photomultipliers in space experiments is described. Each channel embeds 256 memory cells which sample the input information at 200 MS/s. A single cell includes a sampling capacitor, a single-slope analog-to-digital converter and a digital control logic. The digitization is carried out only if a trigger signal validates the time window thus saving power. Moreover, the cells can can be digitized in parallel to speed up the conversion phase. The ASIC is designed in a 65-nm CMOS technology and the target power consumption is 5mW/channel.

Speaker: Silvia Tedesco (INFN Turin)

Tedesco-TWEPP2022.pdf

16:40 A high speed phase locked loop of a pixel readout ASIC for the CSR external-target experiment

We present a high speed Phase Locked Loop (PLL) which is designed to provide high speed clock for a pixel chip to transmit the serial data off chip. The pixel chip is designed to read out the charge of a beam monitor which is part of the CSR external-target experiment at HIRFL in China. The PLL consists of a differential ring oscillator, a digital divider, three-state phase frequency detector, a current charge pump and a second-order loop filter. The simulations show that the output clock frequency is 1.1 GHz or 2.2GHz with a jitter of ~4ps

Speakers: Zhengyu Hu, Chaosong Gao (Central China Normal University)

A high speed phase locked loop of a pixel readout ASIC for the CSR external-target experiment.pdf

Supporting document of A high speed phase locked loop of a pixel readout ASIC for the CSR external-target experiment.pdf

16:40 A high-resolution clock phase shifter circuitry for ALTIROC

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks of 40 MHz, 80 MHz, and 640 MHz in the ALTIROC chip. The phase shifter is a two-step architecture, consisting of a coarse-phase shifting and a fine-phase shifting with a 97.7 ps step. The fine delay is a DLL-based structure operating at 640 MHz. The clocks are programmable independently and share one DLL to save power and area. The phase shifter is fabricated in a 130 nm CMOS process. The DNL and INL are ±0.6 LSB and ±0.75 LSB, respectively. The power consumption is 1.3 mW.

Speaker: Mr Xing Huang (Southern Methodist University)

Phase Shifter of Supporting Document for TWEPP22.pdf

16:40 A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65nm CMOS process. The driver utilizes a three-tap Feed-Forward Equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the Unit Interval (UI) via an 8-stage Delay-Locked Loop (DLL) and digital interpolator (DI). One can also control the output amplitude and source impedance during each UI via a programmable array of eight Source-Series Terminated (SST) drivers. The entire design, consisting of the DLL, two DIs, and three SST driver arrays, consumes 7.2mW from a 1.2V supply (67% from the SST drivers) at 1Gb/s.

Speaker: Mr Nicholas St. John (Brookhaven National Laboratory (US))

LowPower_1Gb_LineDriver_Figures_Nicholas_StJohn.pdf

16:40 A Monolithic Active Pixel Sensor with Node-Based, Data-Driven, Parallel Readout for the High Energy Physics Experiment Vertex Detector

We present the design of a prototype MAPS sensor MIC6 based on a 55 nm Quad-well CMOS Image Sensor process for the high energy physics experiment vertex detector application. A new node-based, data-driven, parallel readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. The size of MIC6 is 2.8 mm × 2.8 mm, which contains a pixel matrix of 64 rows by 64 columns, and the pixel size is 23.6 μm × 20 μm. The integration time is 5us, and the hit arrival time measurement accuracy is 10 ns.

Speakers: Le Xiao (Central China Normal University CCNU (CN)), Mr bihui you

mic6_diagrams.png

mic6_layout.png

MIC6_TWEPP2022.pdf

test_system.png

16:40 BETSEE: Testing for System-Wide Effects of Single Event Errors on ITk Strips Modules

The Inner Tracker silicon strip detector (ITk Strips) is a part of the ATLAS upgrade for the HL-LHC. The detector readout and control is accomplished by the interaction of three on-module custom ASICs (ABCStarv1, HCCStarv1 and AMACstar). All ASICs are designed with protections against Single Event Errors. Their resilience at the system-level can be tested using the Board for Evaluation of Triple-chip Single Event Effects (BETSEE). This special places all three ASICs into the beam-spot concurrently and allows for module-like operation. The results from irradiating BETSEE with heavy ions and protons will be presented.

Speaker: Ryan Roberts (Lawrence Berkeley National Lab. (US))

BETSEE_TWEPP_Poster_v6_fixed.pdf

16:40 CIC a radiation tolerant 65nm data aggregation ASIC for the future CMS tracking detector at LHC

The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. Two versions, CIC1 and CIC2, were tested successfully in 2019 and 2021 respectively. The design, implementation, and preliminary test results of the final version, CIC2.1, are presented.

Speaker: Benedetta Nodari (Centre National de la Recherche Scientifique (FR))

CIC_Twepp_2022_Nodari.pdf

16:40 Clock stability measurements using the Barrel Calorimeter Processor V1

The stability of the clock distributed by the first version of the Barrel Calorimeter Processor (BCP V1) to the front-end electronics has been evaluated and compared with the required performance as specified for the phase 2 upgrade of the CMS Barrel Electromagnetic Calorimeter (EB). The evaluation setup emulated a full clock branch of the planned EB system through multiple stages. The stability of the clock phase and jitter was measured during a long run with no configuration changes as well as many short runs where reconfiguration was applied. Finally, the impact of component temperature variation on the clock was evaluated.

Speakers: Nikitas Loukas (University of Notre Dame (US)), Stephen Goadhouse (University of Virginia (US))

2022_09_20_nloukas_TWEPP.pdf

16:40 Commissioning of the new ATLAS Muon Central Trigger Processor Interface (MUCTPI)

The new Muon-Central-Trigger-Processor-Interface (MUCTPI) is part of the upgrade of the ATLAS Level-1 trigger system for the upcoming run of the Large Hadron Collider at CERN. High-end FPGAs receive and process muon candidate information arriving on 208 high-speed optical serial links, while the board is controlled by a SoC. Processed trigger information and summary data are sent to other parts of the trigger and data acquisition system. This paper describes the hardware setup, the online software as well as the integration and commissioning procedures carried out during the start of LHC Run 3.

Speaker: Aimilianos Koulouris (CERN)

Commissioning of the new ATLAS Muon Central Trigger Processor Interface (MUCTPI).pdf

16:40 Design and characterization of a cascode switching stage for high frequency radiation hardened DC/DC converters for the supply of future pixel detectors

Serial Powering features the upcoming phase II HL-LHC upgrade in the ATLAS and CMS experiment. The conventional approach of placing the pixel modules in a parallel arrangement could not be established due to different limitations like restricted space requirements or radiation tolerance, which makes the design of a suitable DC/DC-converter challenging. To ensure that future DC/DC converters can tolerate high radiation doses at reduced space requirements, a high-frequency switching stage with up to 4 stacked core devices with a related biasing circuit for the implementation in DC/DC-converters was considered and successfully verified in a first prototype.

Speaker: Jeremias Kampkötter

TWEPP_POSTER_2022kampkoetter.pdf

16:40 Design and Digitization Architecture for HPSoC: A very high Channel Density Waveform Digitizer with sub-10ps resolution

We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features: picosecond-level timing resolution; 10 Gs/s waveform digitization rate to allow pulse shape discrimination; moderate data buffering (256 samples/chnl); autonomous chip triggering, readout control, calibration and storage virtualization; on-chip feature extraction and multi-channel data fusion.

Speaker: Dr Luca Macchiarulo (Nalu Scientific, LLC)

16:40 Design and first test results of the CMS HGCAL ECON-T ASIC including an autoencoder-inspired neural network for on-detector data compression

The CMS experiment will replace its endcap calorimeters with a High Granularity Endcap Calorimeter (HGCAL) as part of the upgrades for High Luminosity LHC. The HGCAL readout system includes the Endcap Trigger Concentrator (ECON-T) ASIC to help manage the immense data volume associated with the trigger path of this six-million channel “imaging” calorimeter. Each ECON-T ASIC handles 15.36 Gbps of HGCROC trigger data and performs up to 12x data reduction by means of four user-selectable algorithms for data selection or compression. The design and first test results of the ECON-T ASIC are presented.

Speaker: James Hoff (Fermi National Accelerator Lab. (US))

16:40 Design and preliminary results of a shunt voltage regulator for a HV-CMOS sensor in a 150 nm process

The University of Liverpool HV-CMOS R&D group develops depleted monolithic active pixel sensors (DMAPS) for use in high radiation environments. In this contribution, we will present an overview of results from the latest chip, UKRI-MPW0. The contribution will focus primarily on the design of three sub-circuits, a bipolar junction transistor (BJT) based bandgap reference (BGR), a fully CMOS based bandgap reference and a shunt regulator, and their measurement results. The challenges of the analogue design and how they were solved will be discussed.

Speaker: Samuel Powell (University of Liverpool (GB))

twepp_2022_Poster_A0_portrait_sch.pdf

tweppAbstract_BGRs_EV2_updated3.odt

16:40 Design and prototyping of large-scale flex circuits for the ATLAS ITk Pixel detector

The tight space constraints of the ATLAS ITk Pixel system motivate the design of large-scale flex circuits for carrying low-voltage power, high-voltage sensor bias, and command/data transmission. These circuits extend over long distances in the barrel or large areas in the endcap rings, and they pose unique design challenges. We report on the design and prototyping of large-scale flex circuits for the ATLAS ITk Pixel system, with a focus on technical issues encountered and lessons learned.

Speaker: Graham Miller (University of Manchester (GB))

ITK Pixel Detector TWEPP2022.pdf

ITK Pixel Detector TWEPP2022.pptx

16:40 Development and prototyping of the Versatile Link+ fibre cabling plants for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN

With the foreseen upgrades in HL-LHC, the Versatile Link Plus project was launched to streamline the upgrade of the current optical fibre links between the experiments and the counting room in order to reach higher data rates.

New fiber cabling plants have been designed in this framework for tight integration in experiment front ends and operation at higher radiation doses. These make use of novel multi-fibre assemblies that are tailored to the specific experiment requirements and conditions.

This paper describes the design decisions that have led to the final production-ready prototypes and the related implementation of a large-scale procurement framework.

Speaker: Dr Stefano Meroli (CERN)

TWEPP_Poster_d_3.pdf

TWEPP_Poster_d_3.pptx

16:40 Development of a CompactPCI-Serial Hardware Toolbox for SLS-2.0

Motivated by upcoming large upgrade projects at PSI and due to increasing demands for performance (handling more data, faster processing) in various subsystems of the accelerator and beamlines, our electronics and control system experts had the task to evaluate alternatives to the existing VME technology and build a new portfolio of electronic hardware tools accordingly. CompactPCI-Serial was chosen as the standard platform for building our future modular control and data acquisition systems. We report on the state of the current challenging developments and describe system architectures for building high performance control and data acquisition systems.

Speaker: Mr Patrick Pollet (PSI-Paul Scherrer Institut)

Poster-Developement of a CompactPCI-Serial Hardware Toolbox.pdf

Poster @ LLRF22: CompactPCI Serial Based Generic and Modular Processing Platform at PSI

16:40 Development of a FPGA-based Data Acquisition System (DAQ) for Muon Scattering Tomography

An FPGA-based DAQ has been developed for collecting position information from several position-sensitive RPCs to reconstruct the tracks of cosmic muons in a muon scattering tomography setup. An 8-channel ultra-fast preamplifier discriminator NINO ASIC has been used in the front-end for the acquisition of current signals induced on readout channels of the RPCs. The DAQ has been designed for measuring the Time-Over-Threshold (TOT) property of the NINO ASIC by using a high-frequency clock. The performance of the scheme has been studied by measuring the efficiency of detecting cosmic muon events by a glass RPC in comparison to a plastic scintillator.

Speaker: Mr Subhendu Das (Saha Institute of Nuclear Physics (SINP), India)

16:40 Development of the radiation and magnetic field tolerant DC/DC converter system for the ATLAS ITk Strip Detector.

The custom design, radiation and magnetic field tolerant step-down DC/DC converter system was developed to supply LV power for the ATLAS ITk Strip Detector segments. The system is modular and consists of custom frames with embedded cooling plates and insertable boards containing two or four output channels. Each channel comprises a 48-to-11 V DC/DC converter, hardware overcurrent and overvoltage protection, correction circuitry to compensate for the voltage drops along the cables, and control and monitoring functionality based on the AMAC chip. This contribution presents the design and performance of the DC/DC converters system, including radiation tolerance evaluation.

Speaker: Mateusz Dyndal (AGH UST Krakow)

twepp_dcdc_poster_v2.pdf

16:40 Digital cells radiation hardness study of TPSCo 65nm ISC technology by designing a Ring Oscillator

The CPPM group has long been designing and testing HV-CMOS blocks to complete monolithic chips in various technologies (TJ180, LF150, AMS) in the framework of several collaborations. In 2020, we participated in the MLR1 run in TowerJazz 65 nm technology through CERN’s EP-R&D WP1.2, by designing a ring oscillator test chip. Its aim is to characterize the standard cells of this technology and evaluate their radiation hardness against TID. There were 48 ring oscillators formed of different cells with different sizes and two thresholds. In 2022, characterization, temperature and Xray irradiation tests took place, leading to encouraging results presented here.

Speaker: Pierre Barrillon (Aix Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France)

TJ65_RO_Poster_TWEPP22_v2.pdf

16:40 DTS-100G - A versatile heterogeneous FPGA board for cryogenic sensor readout

Heterogeneous SoC-FPGAs are extremely valuable in custom instrumentation. We present the joint development of the DTS-100G by DESY and KIT. It is built around a Xilinx Zynq Ultrascale Plus and offers all available high-speed transceivers using QSFP28, Firefly28G, FMC, and FMC+ interfaces. The board is not specialized to a single application and can be used as a generic DAQ platform for various physics experiments. DTS-100G was successfully developed, built, and commissioned. ECHo-100k is the first experiment, which will employ the board. This contribution will show the system architecture and explain how DTS-100G is a crucial component in the DAQ chain.

Speakers: Mr Timo Muscheid (Karlsruhe Institute of Technology), Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))

twepp2022_dts100g_poster.pdf

16:40 Electronics for the far-forward CMS muon detector upgrade, ME0

With the High Luminosity upgrade of the LHC we expect increased instantaneous luminosities up to 5x10^34 cm^-2s^-1, or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of the three new muon sub-detectors. The readout electronics for ME0 must be designed to accommodate high data rates and be sufficiently radiation hard to operate close to the beamline. The design and development status of the readout electronics for ME0 will be presented, along with recent results from integration tests performed using the first prototypes.

Speaker: joseph Carlson (University of California Los Angeles (US))

TWEPP2022_me0_electronics.pdf

16:40 First Measurement Results for the front-end circuits of the Ultra-fast High Pitch digitizer System on a Chip (HPSoC) ASIC

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a 564 ps output rise time, and a projected jitter value on the order of 10 ps.
We will report on additional tests when using the 2nd stage VGS, a 20 um thick AC-LGAD, the power consumption, and the digital switched-capacitor back-end.

Speaker: Dr Macchiarulo Luca (Nalu Scientific, LLC)

HPSoC-TWEPP_summary-4-29.docx.pdf

16:40 Global Trigger Versatile Module for ATLAS Phase-II upgrade

ATLAS detector Phase-II upgrade for the High Luminosity Large Hadron Collider (HL-LHC) affects all major ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses the most advanced FPGAs and optical modules to provide high input and output bandwidth and substantial processing power. The Global Trigger Versatile Module (GVM) hosts the new generation of optical modules and FPGAs running at high data rates and other hardware resources needed for the Global Trigger, acting as an auxiliary hardware component used for development, testing and operational purposes within and beyond the Global Trigger.

Speaker: Viacheslav Filimonov (Johannes Gutenberg Universitaet Mainz (DE))

Poster2022-TWEPP_Filimonov_13-09-2022.pdf

16:40 Hamlet: High bAndwidth coMmercial digitizer for hostile EnvironmenT

Hamlet has developed a modular gamma detector that can be operated in a hostile environment. The system is based on a matrix of CsI crystals readout with thermalized SiPM, and a digitizer board designed for the Mu2e electromagnetic calorimeter and customized for this project. Front-end electronics is based on the MUSIC chip, a custom VLSI component developed by the University of Barcelona. The detector is completely modular and up to 20 crystal detectors can be digitized in parallel with a sampling frequency of 200 MHz. Both the detector modules and the digitizer have been qualified against radiation and magnetic field.

Speaker: Franco Spinella (Universita & INFN Pisa (IT))

16:40 Hough transform Software, Firmware, and Hardware investigation for fast tracking in Phase-II LHC upgrades

This study shows a pattern recognition system based on Hough transform implemented on last generations of FPGA families, as the Xilinx UltraScale+. This investigation started from the ATLAS HTT project, and now it is proposed in general for the LHC Phase-II trigger upgrades HEP experiments, especially to those which aim at fast tracking capabilities. We have designed a Hough transform software emulator first, then a firmware synthesizable design has been developed using a low-level HDL description, and finally we have implemented the project into a large FPGA. The software, firmware, and hardware simulations and tests show compatible results.

Speaker: Fabrizio Alfonsi (Universita e INFN, Bologna (IT))

500 words Summary for TWEPP 2022.pdf

16:40 HVTrack: A monolithic HV-CMOS detector for hadron therapy

The hadron therapy is a powerful medical instrumentation for cancer treatment. For the effectiveness of the hadron treatment, it is important to control the energy released by particles for precisely tracking the Bragg peak point. The present contribution refers to the development of a custom detector for proton source characterization. The detector, placed at different distances from the source, has to measure the energy of detected particles and tracking the trajectory of them in order to evaluate possible presence of scattering due to the interaction with the sample.

Speaker: Matthew Franks

Figures.pdf

mfranks_TWEPP22_poster.pdf

16:40 Integration and Commissioning of the ATLAS Tile Demonstrator Module for Run 3

The electronics of the ATLAS Tile Calorimeter will be replaced for the HL-LHC. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated during seven test beam campaigns, and inserted into the ATLAS experiment in 2019. The Demonstrator module was build with backward compatibility with the present ATLAS systems. We present the current status and test results from the demonstrator module running in ATLAS.

Speaker: Humphry Tlou (University of the Witwatersrand (ZA))

ATL-COM-TILECAL-2022-050-tlou.pdf

16:40 Investigations on Hardware Implementable Algorithms for Particle Detector Read Out

In order to meet power and heat budget in large multichannel detector systems, an early data reduction by the means of signal feature extraction is necessary.
We are contributing to this topic, studying different approaches from analog and digital signal processing, investigating the influence of parameters like bandwidth and digitizer resolution. In a second step, we are looking into the influence of the signal parameterization, evaluating algorithms that are suitable for sensors of different characteristics.
We will present our methodology together with first results, showing the capability of common approaches as well as novel ideas.

Speaker: Florian Rössing

TWEPP2022_FlorianRoessing_Poster.pdf

16:40 LHCB PLUME Probe for LUminosity MEasurement

PLUME (Probe for LUminosity MEasurement) is a dedicated luminosity meter (luminometer) for the LHCb detector which will operate during Run 3 at a luminosity level five times higher than in the previous runs. It was designed to measure, in real time, the instantaneous luminosity with an accuracy better than 5 %.
The detector relies on the registration of Cherenkov light emitted by particles passing through an hodoscope composed by small elementary detectors placed upstream the collision region. Each elementary detector is a photomultiplier coupled to a Fused Silica tablet.
The detector, was installed and commissioned January 2022.

Speaker: Olivier Duarte (Université Paris-Saclay (FR))

TWEPP_2022_Abstract_ODuarte_V2.pdf

16:40 LHCb Scintillating Fiber Tracker Front End Electronics Test System

LHCb is undergoing a major upgrade to cope with LHC RUN3's increased luminosities and a trigger-less 40 MHz read-out to improve on many world-best physics measurements. A light and homogeneous tracker based on plastic scintillating fibers (SciFi) driven by 524k SiPM channels is being installed downstream of the LHCb dipole magnet. A Test System is in use to ensure the Quality Control of each of the 256 custom-designed and large-scale produced Front-End Boxes used in this new LHCb tracker. Here we describe the design, assembly, and operation of this Test System and its multiple custom-made electronics modules.

Speaker: Ulisses De Freitas Carneiro Da Graca (CBPF - Brazilian Center for Physics Research (BR))

TWEPP 2022 Figures Annex.pdf

16:40 Modern C++17 Data Pre-Processing HLS Dataflow Template Library

Developing and implementing algorithms for detector read-out using FPGAs is traditionally done by using a hardware description language like VHDL, Verilog, or System Verilog. In the proposed approach here, we discuss an alternative way using higher level languages like the Intel HLS Compiler. Intel HLS supports C++17 standard and is ideal to apply methods from Modern C++ to implement complex algorithms more easily. In this work we have developed a dataflow template library. This enables a shorter development time for increasingly complex algorithm requirements, which is also important for next generation experiments in the future.

Speaker: Thomas Janson (Goethe University Frankfurt (DE))

AbstractMaterial.pdf

TWEPP2022_poster.pdf

16:40 New readout electronics for ATLAS ZDC detector

The ATLAS ZDC detectors located in the LHC tunnel detect far-forward neutrons from interactions during lead-lead collisions. PMT signals are transferred over fast air-core cable at distance of 200 m to electronics room. A new ZDC-LUCROD readout module is a 9U VME board capable of processing signals from 8 channels with an FADC sampling rate of 320 MHz. The primary modification wrt. LUCID-LUCROD is the full integration with ATLAS TDAQ (handling L1A, s-link data transfer, busy) and digital triggering based on pipelined calculation of 2 nd derivative with further processing using a programmable set of thresholds.

Speaker: Krzysztof Marian Korcyl (Polish Academy of Sciences (PL))

TWEPP_2022Abstract.pdf

TWEPP2022_KrzysztofKorcyl_v3.pdf

TWEPP_2022Summary.pdf

16:40 Novel monolithic silicon detector for particle physics

A new concept in charged particle detection is proposed to establish the availability of sensors with high spatial (20 μm) and time resolution (20 ps). The detector consists of a monolithic sensor tightly integrated with an analog front-end in BiCMOS technology. In this contribution, first results of simulations and tests of monolithic sensor made in IHP SG13G2 technology are presented. The readout electronic is implemented on the sensors bulk. The nwell charge collection nodes were reduced to 10 µm by 10 µm in order to evaluate the trade-off between efficiency, charge sharing and timing performance.

Speaker: Ekaterina Trifonova

Screenshot 2022-04-28 at 16.35.12.png

TWEPP_Trifonova.pdf

16:40 Overview of the LHCb Mighty Tracker with focus on the newly developed MightyPix based on HV-CMOS technology

Beyond Run$4$ of the LHC the instantaneous luminosity in the LHCb detector is going to be raised to $1.5\mathrm{x}10^{34}\mathrm{cm}^{-2}\mathrm{s}^{-1}$. To achieve stable operations and precise tracking, it is planned to upgrade the complete LHCb tracking system.
The downstream trackers have to be upgraded to withstand the increased radiation and occupancy at a similar or lower material budget than the current detector. A hybrid solution consisting of scintillating fibres in the outer and HV-CMOS MAPS in the innermost region is under development. The detector with an silicon area of $18\mathrm{m}^2$ will be one of the largest devices built in this technology.

Speaker: Hannah Schmitz (University of Bonn (DE))

16:40 Performance evaluation of the prototype pixel readout chip (CROCv1) for the CMS Inner Tracker Upgrade

Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The CMS pre-production chip CROCv1 was submitted in June 2021 and an extensive characterization campaign has been running since its arrival in October 2021.
This contribution gives a general overview of the chip architecture and discusses the characterization and testing of CROCv1.

Speaker: Yiannis Kazas (Nat. Cent. for Sci. Res. Demokritos (GR))

Poster_Performance_Evaluation_of_CROCv1_final.pdf

16:40 Planar fiber-chip-coupling using angle-polished polarization maintaining fibers

We report on our latest developments of a planar fiber-chip-coupling scheme, using angle polished, polarization maintaining (PM) fibers. Most integrated photonic chip components are polarization sensitive and a suitable way to launch several wavelength channels to the chip with the same polarization is the use of PM fibers. Those impose several challenges at processing and handling to achieve a stable, permanent, and low-loss coupling.
We present the processing of the fibers in detail and experimental results for our planar and compact fiber-chip-coupling technique.

Speaker: Dr Marc Schneider (KIT - Karlsruhe Institute of Technology (DE))

PlanarFiberChipCoupling_Image_v2.jpg

TWEPP2022_Schneider_PlanarFiberChipCouplingUsingAnglePolishedPolarizationMaintainingFibers_LQ.pdf

16:40 Pre-Production Testing of the AMACStar ASIC at Penn for the ATLAS ITk Detector

The high-luminosity upgrade to the LHC (HL-LHC) requires an all new, silicon-based inner detector (ITk strips). The AMACStar is one of three radiation hard ASICs that will be installed on the ITk strip modules. Its function is to autonomously monitor and control the temperatures, voltages, and currents in the detector modules, an essential feature for the ITk detector modules. A comprehensive probe-station testing software and procedure have been developed in order to test the digital and analog functionality of every AMACStar. A detailed grading scheme is then applied to determine which chips should be installed on the modules.

Speaker: Thomas Christopher Gosart (University of Pennsylvania (US))

TGosart_AMACStar_TWEPP2022_Poster_Final.pdf

TGosart_AMACStar_TWEPP2022_Poster_Final_Revised.pdf

16:40 Radiation hard True Single Phase Clock logic for high-speed circuits in 28 nm CMOS

TSPC dynamic logic is widely used in high-speed circuits like high-speed SERDES or frequency dividers. TSPC flip-flops are characterized by their high operation speed and low power consumption when compared with static flip-flops. Due to the relatively high leakage currents in the modern CMOS process, the use of leakage protection techniques of the storage nodes of TSPC logic is mandatory. In this paper Single Event Upsets (SEU) are investigated by quantifying the critical charge needed to upset the leakage protected TSPC flip-flops. The results are compared to both the static and traditional TSPC circuits without leakage mitigation.

Speaker: Adam Klekotko (CERN/KU Leuven)

poster.pdf

Radiation hard True Single Phase Clock logic for high-speed circuits in 28 nm CMOS.docx

16:40 Radiation hardness and timing performance in MALTA monolithic Pixel sensors in Tower 180 nm

The MALTA family of DMAPS produced in Tower 180 nm CMOS technology target radiation hard applications for the HL-LHC and beyond. Several process modifications and front-end improvements have resulted in radiation hardness up to 2e15 n/cm² and time resolution below 2 ns, with uniform charge collection efficiency across the Pixel of size 36.4 x 36.4 um² with a 3 µm² electrode size. The MALTA2 demonstrator produced in 2021 on high-resistivity epitaxial silicon and on Czochralski substrates implements a new cascoded front-end that reduces the RTS noise and has a higher gain. This contribution will show results from MALTA2.

Speaker: Abhishek Sharma (CERN)

ASharma_Poster-TWEPP2022.pdf

16:40 RD50-MPW3: A fully monolithic digital CMOS sensor for future tracking detectors

The CERN RD50 CMOS working group develops the RD50-MPW series of monolithic CMOS sensors for potential use in future high luminosity experiments such as HL-LHC and FCC-hh.
In this contribution, we will present an overview of the RD50 High Voltage-CMOS activities, focusing on the design of RD50-MPW3, the latest chip of this series, and the readout electronics beyond the chip. We will give a detailed overview of the pixel matrix and the digital peripheral readout. We will discuss the challenges the design presented and how we solved them, together with the first laboratory evaluation results of the chip.

Speaker: Patrick Sieberer (Austrian Academy of Sciences (AT))

Poster_V5.pdf

16:40 Script-Assisted Board Layout for the CMS HGCAL Readout Electronics

The CMS Phase II High-Granularity Calorimeter (HGCAL) relies on passive boards known as wagons to transmit signals from silicon sensor modules to upstream electronics for further processing. Such wagon boards face many design constraints that result in over 50 unique varieties, each of which requires the precise placement of dozens of components onto a PCB layout. A suite of tools has been developed to both algorithmically compute all required board varieties and to then automate the placement of all components onto a layout, greatly simplifying the design process and reducing the work needed to be done by hand.

Speaker: Devin Mahon (University of Minnesota (US))

TWEPP2022Poster.pdf

16:40 Single-event effects calibration using two-photon absorption and a CMOS image sensor

A two-photon absorption (TPA) laser setup can nowadays be used to imitate radiation effects of high-energy particles by tightly focusing an ultrafast laser on a sensitive node of electronics. At a certain energy per pulse, a single-event effect (SEE) can occur. This paper proposes to measure the amount of electron-hole pairs generated in the component and the characteristics of the laser beam through a CMOS image sensor. This method allows better calibration of the TPA setup and makes the setup more representative for the radiation conditions. This information can then be used to predict or prevent SEE in electronics.

Speaker: Daan Blommaert

Images_Abstract_TWEPP_2022 - Single-event effects calibration using two-photon absorption and a CMOS image sensor.pdf

Poster 'Single-event effects calibration using two-photon absorption and a CMOS image sensor' .pdf

16:40 Sub-10ps resolution TDC with dithering in 28nm CMOS technology for future 4D trackers

Precision timing at 10ps levels will be transformative at future collider experiments. In case of high-energy, high-luminosity hadron colliders, including Run5/6 upgrades of HL-LHC, an integrated four-dimensional tracker with timing resolution of 10-30ps can drastically reduce the combinatorial challenge of track reconstruction at very high pileup densities. 4D trackers and timing layers are also expected to play important roles at future muon, electron-positron, and electron-ion colliders. As one of the critical circuit blocks necessary to enable 4D operation in trackers we present the design of 6.25ps resolution Time-to-Digital Converter in 28nm CMOS technology that implements dithering to improve conversion linearity.

Speaker: Bojan Markovic (SLAC National Accelerator Laboratory (US))

28nm TDC TWEPP 2022 poster final.pdf

16:40 System Design and Prototyping for the CMS Level-1 Trigger at the High-Luminosity LHC

For the High-Luminosity Large Hadron Collider, the trigger and data acquisition system of the CMS experiment will be entirely replaced. Novel design choices have been explored, including ATCA prototyping platforms with SoC controllers and newly available interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger analyses will be performed through sophisticated algorithms, including widespread use of Machine Learning, in large FPGAs, such as the Xilinx Ultrascale family. The system will process over 50 Tb/s of detector data with an event rate of 750 kHz. We describe system design and prototyping and review trigger algorithm exemplars.

Speaker: Christian Herwig (Fermi National Accelerator Lab. (US))

poster_v2.pdf

16:40 Test system for the PS Front-End Hybrid High Voltage filter for the CMS Phase-2 Outer Tracker Upgrade

As part of the CMS Phase Two Outer Tracker upgrade, a test card was developed to test the sensor bias high voltage filters present in the PS-FEH-R hybrids. The test card can test up to four hybrids at the same time. The test functions are voltage measurement, leakage current measurement and resistance measurement. A software test procedure was written to control the card and to perform the data acquisition.

Speaker: Kevin Schleidweiler (Ministere des affaires etrangeres et europeennes (FR))

16:40 The CBM-TRD Cluster Finder

This contributions presents the implementation of the CBM-TRD cluster finder. The cluster finder is implented with Vitis HLS in an FPGA.
The CBM experiment at FAIR will focus on rare probes of the QCD phase diagram at high net-baryon densities.
The free streaming DAQ has to process up-to 2 TB/s of raw data. This data undergo online event selection, where 4D track reconstruction is necessary. To accelerate the online event selection, the data is preprocessed in the FPGA.
I will demonstrate how HLS can be utilized to implement a high-throughput cluster-finder capable of processing up-to six 4.8 GB/s GBT-Links.

Speaker: David Schledt (IRI - Frankfurt University)

poster_paths.pdf

16:40 The Design and Testing of the COLDATA Concentrator ASIC for the Deep Underground Neutrino Experiment

COLDATA is the data concentrator ASIC for the Liquid Argon Time Projection Chamber (LArTPC) Far Detector of the Deep Underground Neutrino Experiment (DUNE). This ASIC will operate for its lifetime at cryogenic temperatures immersed in LAr. Two COLDATA, eight ColdADC, and eight LArASIC front-end ASICs are placed on each Front-End Motherboard (FEMB) in the LArTPC. Each COLDATA concentrates the data output from four ColdADC ASICs (64 front-end channels) onto two 1.25 GHz serial lines. The COLDATA also provides clock generation and control, slow and fast command response, and reset control for the Front-End Motherboard.

Speaker: James Hoff (Fermi National Accelerator Lab. (US))

Abstract and Summary_V2.pdf

Diagrams.pdf

16:40 The irradiation test and upgrade of the Gigabit Transceiver For The ATLAS Inner Tracker Pixel Detector Readout Upgrade

This paper presents the irradiation test results and a revised design of a gigabit transceiver, GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. The GBCR includes 7 receiver channels operating at 1.28 Gbps and two 160 Mbps transmitter channels. The transmitter and receiver channels connect to the front-end readout chip via 34-American Wire Gauge (AWG) twin-axial cables up to 5 meters and a 1-meter flex cable. After we found the chip was SEE sensitive in an irradiation test, we submitted a revised design in February and expected to get the test results this summer.

Speaker: Li Zhang

GBCR_supporting document_v2.docx

16:40 The monolithic ASIC of the high-resolution pre-shower of the FASER experiment

A high resolution W-Si preshower detector is proposed for the FASER experiment at CERN to enable the measurement of new physics signals related to Long Lived Particles. For this purpose, a 1.5x2.2 cm2 monolithic silicon active-pixel detector is being developed. The detector will integrate ultra-fast, low-noise front-end electronics in 65 μm side hexagonal pixels. The system is designed to read out thousands of pixels per event. Three pre-production ASICs in 130 nm SiGe BiCMOS technology were submitted for fabrication to test the best design solution for the final chip.

Speaker: Fulvio Martinelli (Universite de Geneve (CH))

17:00 Trigger-less readout and unbiased data quality monitoring of the CMS Drift Tubes muon detector

The CMS experiment 40MHz Scouting project is aimed at intercepting the data produced at the level of the detectors' front-end without the filters induced by hardware-based Triggers. A first 40MHz Scouting implementation is realized by reading a slice of the Drift Tube (DT) muon detector, equipped with so-called Phase-2 Upgrade front-end boards. The data are transferred via high-speed optical links to back-end boards independently from the central DAQ, permitting to monitor in real-time the detectors' status spying all the signals produced at the front-end level, and providing an unbiased estimate of the CMS DT hit-rate under various data-taking conditions.

Speaker: Jacopo Pazzini (Università e INFN, Padova (IT))

Triggerless_Readout_CMS_DT_DQM_pazzini_TWEPP2022.pdf

18:30 → 21:30 Social activities

Wednesday, 21 September

09:00 → 10:00 ASIC

Conveners: Christine Guo Hu (Centre National de la Recherche Scientifique (FR)), Ping Gui

09:00 Development of a Stitched Monolithic Pixel Sensor prototype (MOSS chip) towards the ITS3 upgrade of the ALICE Inner Tracking System

The MOnolithic Stitched Sensor chip (MOSS) is a development prototype towards the innovative ITS3 vertexing detector for the ALICE experiment at the LHC. Designed using a 65 nm CMOS Imaging technology, it aims at profiting from the stitching technique to construct a single-die monolithic pixel detector of 1.4 cm x 26 cm. The MOSS chip is one of the prototypes developed within CERN-EP R&D to learn how to make stitched wafer-scale sensors with satisfactory yield. This contribution will describe the challenges encountered and some of the techniques adopted in the design of the chip.

Speaker: Pedro Vicente Leitao (CERN)

20220921.PL.MOSS.TWEPP2022.pdf

09:20 Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm ISC CMOS imaging technology

A series of monolithic active pixel sensor prototypes were manufactured in the TPSCo 65 nm ISC imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4x4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel sizes (10um - 25um), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements.

Speaker: Wenjing Deng (Central China Normal University CCNU (CN))

TWEPP_APTS_bk.pdf

09:40 Monolithic pixel sensor design for picosecond-level time resolution: the MONOLITH ERC project

The MONOLITH ERC Advanced project aims at producing a monolithic silicon pixel ASIC with picosecond-level time stamping by using fast SiGe BiCMOS electronics and a novel sensor concept, the Picosecond Avalanche Detector (PicoAD). A first ASIC prototype, featuring fast electronics and hexagonal pixel with 100µm pitch, confirms that the PicoAD principle works and achieves time resolutions better than 20ps. Tests on the electronics and sensor optimization have driven to a new ASIC design with improved electronics and 50µm pixel pitch, aiming to a time resolution below 10ps. The architecture, simulations and measurements will be presented.

Speaker: Antonio Picardi (Universite de Geneve (CH))

TWEPP22_conference_Antonio_Picardi_MONOLITH.pdf

09:00 → 10:00 Programmable Logic, Design Tools and Methods

Conveners: Johan Alme (University of Bergen (NO)), Salvatore Danzeca (CERN)

09:00 DART28-FPGA implementation study for future high-speed links

The data link from the detectors to the back-end stage must keep up with the requirements from the upcoming generation of High Energy Physics experiments. Pushing the limit of the Non-Return-to-Zero (NRZ) modulated signals, a line rate of up to 28 Gbps can be realized. In this talk, the implementation of the DART28 demonstrator system based on FPGA platforms from Xilinx and Intel will be presented. The performance characteristic of these links will be discussed, and the Forward Error Correction (FEC) performance will be compared to that of an ideal model.

Speaker: Chaowaroj Wanotayaroj (CERN)

PAM4Eval - TWEPP2022.pdf

PAM4Eval - TWEPP2022.pptx

09:20 Developments in hls4ml and its application

Neural Network (NN)-based inference deployed in FPGAs or ASICs is a powerful tool for real-time data processing and reduction. FPGAs or ASICs may be needed to meet difficult latency or power efficiency requirements in data acquisition or control systems. The software package, hls4ml, was designed to make deploying optimized NNs on FPGAs and ASICs accessible for domain applications. We will discuss recent improvements and applications, and discuss our recent collaboration with the AMD/Xilinx FINN group to develop a Quantized ONNX (QONNX) representation to serve as a common way to to represent quantized NNs.

Speaker: Jovan Mitrevski (Fermi National Accelerator Lab. (US))

hls4ml TWEPP.pdf

09:40 Integration of FPGA RDMA into the ATLAS Readout with FELIX in High Luminosity LHC

The FELIX system is used to interface the front-end electronics and the commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. In the current version of FELIX, RDMA communication is implemented using software on both ends of the links. Improvements of the data throughput as part of the High Luminosity LHC upgrade, by implementing RDMA support in the front-end FELIX FPGA, have been tested. Now, a version of FELIX that uses the FPGA implementation of RDMA is being proposed and demonstrated.

Speaker: Matei Vasile (IFIN-HH (RO))

TWEPP_2022_Matei.pdf

TWEPP2022-presentation-final.pdf

10:00 → 10:30 Coffee break

10:30 → 11:15 Invited

Convener: Johan Alme (University of Bergen (NO))

TWEPP-2022_UVVM.pptm

10:30 UVVM (Universal VHDL Verification Methodology) - The world-wide #1 for VHDL verification - Made in Norway

The UVVM (Universal VHDL Verification Methodology) is the fastest growing FPGA verification methodology world-wide - independent of language, and number 1 for VHDL. Furthermore, VHDL is used by 50% of all FPGA designers, and between 80% and 90% of all FPGA designers in Europe. Thus UVVM has become a very important verification methodology for FPGA designers, and in fact also for quite a few ASIC designers. And UVVM is made in Norway.

The fast growth and popularity is primarily due to the improvement that UVVM yields in both FPGA quality and development time. This open-source Library and Methodology has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner providing modularity, reusability, constrained-random stimulus and functional coverage similar to UVM, but all in a way familiar to VHDL designers. UVVM also has the largest library of open source VHDL verification models and components. With more than 50% of all FPGA designers using VHDL, UVVM provides a great verification solution for these users.

This presentation will first try to explain to non-FPGA designers what this is all about; - FPGA, Verification, UVVM...
Then we will go more into detail and show you how UVVM works and how it significantly helps on quality and efficiency through readability, maintainability, debuggability and reuse.

---

Espen Tallaksen is the CEO of EmLogic, a leading design centre for Embedded Systems and FPGA in Norway.
He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway.

During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is the #1 VHDL verification methodology and library world-wide, and in fact the fastest growing FPGA verification methodology independent of HDL.

He has given many presentations internationally on various technical aspects of FPGA development, including lots of hands-on tutorials and keynotes, all with a crowded audience and great feedback. He is also giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality.

Speaker: Espen Tallaksen

TWEPP-2022_UVVM.pptm

11:20 → 12:20 ASIC

Conveners: Ping Gui, Marcus Julian French (Science and Technology Facilities Council STFC (GB))

11:20 MiniCactus : a HV-CMOS monolithic timing sensor with sub 100 ps resolution

MiniCACTUS is a monolithic CMOS sensor designed for tagging Minimum Ionizing Particles at the 100 ps level. The sensor features an array of diodes, without internal amplification, of surface 1.0 mm² and 0.5 mm², with an analog front-end and discriminator per pixel. A time resolution of 88 ps has been measured on a 0.5 mm² pixel from a 200 µm-thick sensor tested at CERN. 300 micron and 200 micron sensors with optimized FE parameters and increased bias voltage will be tested May-July 2022. Significant improvements on the timing resolution, already checked in lab, are expected.

Speaker: Fabrice Guilloux (Université Paris-Saclay (FR))

2022-09-21_TWEPP_MiniCactus_v2.1-small.pdf

TWEPP_2022_additional_file.docx

11:40 FLAME SoC readout ASIC for electromagnetic calorimeter

The design and measurement results of a SoC readout ASIC, called FLAME, developed for the electromagnetic calorimeter at the future linear collider are presented. The FLAME consists of 32 channels with variable gain front-end, fully differential shaper, and a 10-bit SAR ADC, working at 20 MSps, in each channel. All ADC samples are streamed out by two 5.2 Gbps serializers. Two testbeam campaigns with FLAME-based readout have been conducted successfully. The testbeam results as well as detailed characterization of the FLAME performed with a dedicated test setup are presented and discussed.

Speaker: Jakub Moron (AGH University of Science and Technology (PL))

moron_TWEPP_2022_09_21.pdf

12:00 A Study for a Radiation Tolerant SoC EcoSystem based on Open Source RISC-V hardware for future High Energy Physics applications

The increase in the complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes are strong advocators for employing a System-on-Chip (SoC) design integration methodology. This contribution will present a survey of open-source RISC-V based SoC design platforms and the results of an evaluation study in terms of performance, power and area of three selected RISC-V SoCs. Finally it will propose a Radiation Tolerant SoC interconnect and associated RISC-V core for low performance, low power, fault-tolerant control and monitoring embedded applications.

Speakers: Marco Andorno (CERN), Risto Pejasinovic (CERN)

20220921_twepp.pdf

20220921_twepp.pptx

11:20 → 12:20 Programmable Logic, Design Tools and Methods

Conveners: Johan Alme (University of Bergen (NO)), Salvatore Danzeca (CERN)

11:20 Evaluation of GBT-FPGA for Timing and Fast Control in CBM experiment

Timing and Fast Control (TFC) system for the Compressed Baryonic Matter (CBM) experiment is being developed with focus on low and deterministic data transmission latency. This helps to avoid congestion of the free-streaming Data Acquisition System (DAQ) system during occasional data bursts caused by the expected beam intensity fluctuations. Proven in latency-optimized experimental data transport applications, the GBT-FPGA core is expected to positively contribute to the TFC system performance. In this work, the core has been integrated as the primary communication interface and its effect on transmission latency and quality of time distribution has been evaluated.

Speaker: Vladimir Sidorenko

twepp22_sidorenko_3.pdf

11:40 An FPGA-based readout chip emulator for the CMS ETL detector upgrade

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the functions of four Endcap Layer Readout Chips (ETROCs), each including a PLL, a fast command decoder, the pixel and global data readout, and an I2C target. Based on the actual ETROC design, the firmware is implemented and preliminarily verified. The emulator board is being used for the ETROC digital design verification as well as for the system development before ETROC is available.

Speaker: Jinyuan Wu (Fermi National Accelerator Lab. (US))

ETROCemulator slides20220921.pdf

ETROCemulator slides20220921.pptx

ETROCemulator supporting doc.pdf

12:00 Embedded Neural Networks on FPGAs for Real-Time Computation of the Energy Deposited in the ATLAS Liquid Argon Calorimeter

At the HL-LHC, the number of proton-proton collisions in one bunch-crossing (called pileup) increases significantly, putting more stringent requirements on the LHC detectors electronics and real-time data-processing capabilities. The ATLAS LAr calorimeter measures with an excellent resolution the energy of particles produced in LHC collisions. The energy is computed in real-time using optimal filtering (OF) algorithms running on dedicated data-acquisition electronic boards based on FPGAs. However, with the increased pileup, the performance of these algorithms decreases significantly. Dedicated Neural networks (NNs) are found to outperform the OF algorithms. The architecture, performance, and firmware implementation for these NNs will be presented.

Speaker: Georges Aad (CPPM, Aix-Marseille Université, CNRS/IN2P3 (FR))

certificate2022_aad.pdf

twepp2022.pdf

13:00 → 14:00 Lunch

14:00 → 15:00 Radiation Tolerant Components and Systems

Conveners: Salvatore Danzeca (CERN), Ken Wyllie (CERN)

14:00 Fab-to-fab and run-to-run variability in 130nm and 65nm CMOS technologies exposed to ultra-high TID

The discovery of a large fab-to-fab variability in the TID response of the CMOS technologies used in the design of ASICs for the particle detectors of the HL-LHC triggered a monitoring effort to verify the consistency of the CMOS production process over time. As of 2014, 22 chips from 3 different fabs in 130nm CMOS technology and 10 chips from 2 different fabs in 65nm CMOS technology have been irradiated to ultra-high doses, ranging from 100 $\mathrm{Mrad(SiO_2)}$ to 1 $\mathrm{Grad(SiO_2)}$. This unprecedented monitoring effort revealed significant fab-to-fab and run-to-run variability, both dependent on the characteristics of the MOS transistors.

Speakers: Mr Gennaro Termo (École polytechnique fédérale de Lausanne (EPFL), Lausanne, Switzerland), Mr Gennaro Termo (École Polytechnique Fédérale de Lausanne (EPFL))

TWEPP_2022_Variability.pdf

14:20 Irradiation testing of ASICs for the ATLAS HL-LHC Upgrade

For the high luminosity upgrade to the LHC, the ATLAS inner detector will be replaced by an all-silicon tracker (ITk) consisting of two systems: pixels and strips. The HCCStar and AMACStar are ITk strips ASICs vital for performing the system readout, and monitoring and control.To ensure these ASICs will successfully operate in the high-radiation environment of the HL-LHC, these ASICs need to be tested for radiation tolerance, and this has been tested using both heavy ions and protons. The ASIC designs were shown to be protected against radiation related effects.

Speaker: Andie Wall (University of Pennsylvania (US))

Irradiation testing of ASICS for the ATLAS HL-LHC Upgrade.pdf

14:40 Measurements of Total Ionizing Dose Effects and Influence of NMOS Bulk Bias on a CMOS Image Sensor process

The CERN EP R&D WP 1.2 aims to develop state-of-art monolithic pixel detectors using accessible modern CMOS processes. The TPSCo 65nm process is a suitable candidate and its radiation tolerance and sensor performance are therefore being studied. The impact of the back bias on the transistor behavior has also been measured to provide the designers with accurate models. This process shows sensitivity to radiation and degradation mechanisms similar to previously studied 65nm CMOS technologies, strongly dependent on geometry. In this paper, we offer a qualitative characterization of this node that can serve as a guideline for designers of this technology.

Speaker: Ana Dorda Martin (KIT - Karlsruhe Institute of Technology (DE))

Twepp.pdf

Twepp.pptx

14:00 → 15:00 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR)), Alex Kluge (CERN)

14:00 SAFIR a PET-insert for MRI

SAFIR (Small Animal Fast Insert for MRI) is a PET (Positron Emission Tomography) insert for the Bruker BioSpec 70/30 pre-clinical MRI (Magnet Resonance Imaging) system. It is aiming at truly simultaneous PET/MRI acquisitions allowing imaging time frames of seconds instead of minutes. SAFIR is intended for operation at up to 500MBq injected activities in mice, 10x higher than in other systems. All electronics including power conversion are integrated inside the bore of the 7T MRI magnet. The system achieves a coincidence resolving time of ~220ps FWHM at 511keV. Imaging in mice and rat was successfully performed.

Speaker: Dr Werner Lustermann (Institute for Particle Physics and Astrophysics, ETH Zurich)

award2022_lustermann.pdf

SAFIR_additional_material2.docx

TWEPP_2022_SAFIR_WLustermann_v2.pdf

14:20 AGIPD systems: performance optimization challenges and new developments.

AGIPD is one of the detectors developed for the experimental stations of the European XFEL, one of the newest free-electron laser sources. The detector pixels write high dynamic images from single up to 10⁴ 12.5 keV-photons at a maximum frequency of 4.5 MHz operating in a burst mode – read-out is performed between the bursts. There are certain challenging optimizations done to the different detector blocks, like ASIC and back-end electronics since its commissioning in 2017. Details and results as well as latest developments will be reported.

Speaker: Dr Alexander Klujev (Deutsches Elektronen-Synchrotron)

klujev_twepp2022.pdf

14:40 Development and readout of novel Hybrid Detector for Microdosimetry (HDM)

HDM is a new Hybrid Detector for medical application combining a tissue equivalent microdosimeter and a LGAD-based (Low Gain Avalanche Diode) particle tracker with the goal of improving the radiation quality description. Energy deposition information after analog processing is recorded with 3 ADC mounted on a FPGA based solution, while tracking information is processed by a dedicated readout chip mounted on a custom board and finally processed thanks to FPGAs based solution. This design results in 284 channels (one per LGAD strip) sharing complementary information with the energy deposited in the microdosimeter.

Speaker: Enrico Pierobon

award2022_pierobon.pdf

TWEPP2022_Pierobon_extended.pdf

TWEPP2022_Pierobon.pptx

15:00 → 15:30 Coffee break

15:30 → 16:10 Radiation Tolerant Components and Systems

Conveners: Salvatore Danzeca (CERN), Ken Wyllie (CERN)

15:30 Single Event Effects Testing and Verification of the RD53 Pixel Chip

Single Event Effects (SEE) immunity is one of the major challenges that the RD53 chip is required to meet as being the next generation of the pixel readout chips for the High Luminosity LHC upgrade. Extensive proton and heavy ion beam testing was done to examine the overall chip reliability. The critical analog IP blocks are tested with a Two-Photon Absorption laser and gave an in-depth SET sensitivity analysis of the chip analog bottom. Besides the various testing methods, the substantial verification simulation done at the RTL and the gate level was the essential part of the SEU robustness validation.

Speaker: Jelena Lalic (CERN)

Presentation_RD53_SEE_JL.pdf

SingleEventEffectsRD53.pdf

15:50 Radiation effect evaluation of digital building blocks in a 28 nm CMOS technology

The 28nm bulk CMOS technology is a promising candidate as most advanced node for future design in the High Energy Physics (HEP) community. Three ASICs have been designed to evaluate performances and radiation tolerance, both against Single Event Effects and Total Ionizing Dose, of the digital standard cells libraries and foundry SRAMs. This contribution aims at presenting the custom-developed structures together with the obtained test results, providing crucial information for assessing the sensitivity of this technology to extreme radiation environment and allowing designers to take adequate mitigations techniques in this technology node.

Speaker: Gianmario Bergamin (CERN)

award2022_bergamin.pdf

presentation_28nm.pdf

presentation_28nm.pptx

15:30 → 16:10 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR)), Alex Kluge (CERN)

15:30 The readout system for the tracker of the High-Energy Particle Detector on board the CSES-02 satellite

The High Energy Particle Detector (HEPD-02), part of the CSES-02 satellite, is a compact particle
detector composed by a 3-layer pixel silicon tracker and a calorimetric system.
HEPD-02 will be the first spaceborne instrument using Monolithic Active Pixels (MAPS) in place of micro-strips detectors;
the tracker is composed of 150 CMOS 180 nm sensors, based on the development carried out for the ALICE ITK-2 at CERN.
The stringent requirement in term of power budget and computational power available on a satellite required the development of a custom readout system implementing a sparsified readout architecture implemented on a single low-power FPGA.

Speaker: Giuseppe Gebbia (on behalf of the CSES-Limadou collaboration)

TWEPP.pdf

15:50 The Mu2e electromagnetic calorimeter: readout electronic and qualification

The readout system of the Mu2e electromagnetic calorimeter is composed of a front-end which collects and transmits the SiPM signals to a waveform digitizer performing a 200 MHz sampling. The Mu2e harsh operational environment (Total Ionizing Dose (TID) of 12 krad and neutron fluence of 5x1010 n/cm2 @ 1 MeVeq (Si)/y, 1T magnetic field, level of vacuum of 10-4 Torr) has made the design particularly challenging. We report on the design, specifications, architecture, and results of the qualification test.

Speaker: Elena Pedreschi (Universita & INFN Pisa (IT))

The Mu2e electromagnetic calorimeter readout electronic and qualification.pdf

16:20 → 18:00 FPGA Working Group

Conveners: Ken Wyllie (CERN), Salvatore Danzeca (CERN)

16:20 Introduction

Speakers: Ken Wyllie (CERN), Salvatore Danzeca (CERN)

16:30 CrateBo, an FPGA radiation-testing platform

Speakers: Panagiotis Gkountoumis (Boston University (US)), Salvatore Danzeca (CERN)

CRaTeBo_TWEPP.pdf

CRaTeBo_TWEPP.pptx

16:50 Experience with the GateMate FPGA

Speakers: Rudy Ferraro (Universita e INFN sezione di Napoli (IT)), Salvatore Danzeca (CERN)

17:10 Radiation testing of the PolarFire FPGA on the CMS-Muon OBDT

Speakers: Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES)), Ignacio Redondo Fernandez (CIEMAT)

DT_twepp_CHARM.pdf

DT_twepp_CHARM.pptx

16:20 → 18:00 MIC Working Group

Convener: Kostas Kloukinas (CERN)

16:20 Welcome

Speaker: Kostas Kloukinas (CERN)

MUG TWEPP2022 Kloukinas agenda copy.pdf

MUG TWEPP2022 Kloukinas agenda copy.pptx

16:30 CERN ASIC support news - EP R&D WP5 developments

Speaker: Alessandro Caratelli (CERN, EPFL)

2022.09.14_ASIC-Support_news_and_EP-WP5_developments.pdf

17:00 CERN CHIPS service news

Speaker: Gianmario Bergamin (CERN)

CHIPS_TWEPP.pdf

CHIPS_TWEPP.pptx

17:10 EUROPRACTICE IC services and foundry news

Speaker: Paul Malisse (IMEC)

17:30 EUROPRACTICE EDA tools for the HEP community

Speaker: Mark Willoughby (STFC UK)

17:50 Open Discussion

16:20 → 18:00 Opto-electronics Working Group

Convener: Francois Vasey (CERN)

16:20 Introduction

Speaker: Francois Vasey (CERN)

VLplus_Vasey_TWEPP_21Sep2022.pdf

16:30 Firefly transceivers: roadmap and Q&A (Samtec)

Speakers: Joe Phillips, Josh Cornelius

Samtec _ TWEPP Conference September 2022.pdf

17:00 VTRx+: status and Q&A

Speaker: Csaba Soos (CERN)

VLplus_OptoWG_TWEPP2022.pdf

17:20 VL+ optical cords and cables: status, procurement framework and Q&A

Speaker: Stefano Meroli (CERN)

OPTIFIB_TWEPP2022_USERGROUP_WP5_Sep2022_v1.pdf

OPTIFIB_TWEPP2022_USERGROUP_WP5_Sep2022_v1.pptx

16:20 → 18:00 Power Working Group

Conveners: Hucheng Chen (Brookhaven National Laboratory (US)), Magnus Hansen (CERN)

16:20 ATLAS ITk Pixel serial power chain test and power supply specification

Speaker: Matthias Hamer (University of Bonn (DE))

21092022_twepp22_mhamer_itkpixelpowering.pdf

16:40 CMS IT serial power chain test and power supply specification

Speaker: Simone Paoletti (Universita e INFN, Firenze (IT))

20220920TWEPP-CMS_ITPower.pdf

17:00 CMS Phase-II upgrade power supply needs and procurement (Calo, BTL/ETL, HGCal; 400VDC etc.)

Speaker: Krzysztof Stachon (ETH Zurich (CH))

2022_09_19 - TWEPP2022_CMS_power_distribution.pdf

2022_09_19 - TWEPP2022_CMS_power_distribution.pptx

17:20 ATLAS Phase-II upgrade power supply needs and procurement (Muon, Calo, Strip, HGTD etc.)

Speakers: Agostino Lanza (INFN - Sezione di Pavia), Agostino Lanza (Pavia University and INFN (IT))

twepp2022_ATLAS-PowerSystems_lanza.pdf

twepp2022_ATLAS-PowerSystems_lanza.pptx

17:40 Proposal of power supply testing services

Speakers: Vincent Bobillier, Vincent Bobillier (CERN)

PSservice_TWEPP2022.pdf

PSservice_TWEPP2022.pptx

19:00 → 22:00 Conference dinner

Thursday, 22 September

09:00 → 10:00 ASIC

Conveners: Ping Gui, Christine Guo Hu (Centre National de la Recherche Scientifique (FR))

09:00 A simulation methodology for verification of transient fault tolerance of ASICs designed for high-energy physics experiments

Transient fault tolerance verification is a crucial step in the design of radiation-tolerant ASICs for high-energy physics experiments. In this paper, we discuss a methodical approach toward the verification of transient fault tolerance of ASICs using industry-standard methodologies and tools. The framework for fault verification includes tools for fault enumeration, fault injection, and running fault campaigns. The framework supports fault verification at various levels of design abstraction from high-level register-transfer models to gate-level netlist. The methodology and framework described in this paper were successfully used to identify SEE vulnerabilities in some of the ASICs designed at CERN.

Speaker: Matteo Lupi (CERN)

twepp22_apulli_mlupi.pdf

09:20 Analog IP Blocks in 28nm CMOS for the High Energy Physics Community

A bandgap voltage reference, an 8-bit binary-weighted Digital to Analog Converter (DAC), a rail-to-rail operation amplifier and a scalable low voltage signaling (SLVS) transmitter and receiverhave been developed as macro blocks in 28 nm CMOS technology for the future upgrades for the high luminosity LHC. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in high energy physics will be discussed in the contribution along with characterization results.

Speaker: Franco Nahuel Bandi (CERN)

twepp_slides_2022.pdf

09:40 Radiation-Tolerant All-Digital Clock Generators for HEP Applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, All-digital Phase Locked Loop (PLL) and Clock and Data Recovery (CDR) architectures constitute a promising option for future High Energy Physics (HEP) experiments. Both LC-oscillator as well as a ring oscillator based All-Digital front-end PLL/CDR blocks were studied, designed, manufactured and characterized. The design process, important radiation hardening considerations, as well as the performance obtained with these circuits will be presented in this talk.

Speaker: Stefan Biereigel (CERN)

certificateTwepp2022_biereigel.pdf

TWEPP2022__Radiation_Tolerant_All_Digital_Clock_Generators_for_HEP_Applications.pdf

09:00 → 10:00 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR)), Alex Kluge (CERN)

09:00 Pixel detector hybridisation and integration with Anisotropic Conductive Films

A cost-effective single-die pixel-detector hybridisation technology based on Anisotropic Conductive Films (ACF) is under development, to replace fine-pitch bump bonding with thermo-compression of conductive micro-particles embedded in an epoxy film. It can also be used for the integration of hybrid or monolithic detectors in modules, replacing wire bonding or solder-bumping techniques. An in-house Electroless Nickel Immersion Gold (ENIG) plating process is being developed for single-die chips to achieve the required topology of the pixel pads. This contribution introduces the ENIG and ACF processes, and shows first test results from Timepix3 hybrid pixel assemblies.

Speaker: Janis Viktor Schmidt (CERN and KIT - Karlsruhe Institute of Technology (DE))

220922_TWEPP.pdf

220922_TWEPP.pptx

09:20 Design and testing of long Flexible Printed Circuits for the ATLAS High Granularity Timing Detector demonstrator

The High Granularity Timing Detector for the ATLAS upgrade is under construction to meet the challenges of the HL-LHC. In order to connect a module, the basic detector element, to the surrounding peripheral electronic board, a flexible printed circuit (FPC) is proposed as an interconnection for data transmission and power distribution. Identical design for the FPC is required except their length, depending on the module positioning on the detector active area.The design and qualification of the FPC, manufactured in 13 different lengths (from 28.5 to 73.2$~$cm), are presented.

Speaker: Maria Robles

HGTD_flextails_twepp22.pdf

HGTD_RoblesM_TWEPP22.pdf

09:40 Development of novel low-mass module concepts based on MALTA monolithic pixel sensors

Multi-chip modules using the MALTA1 pixel sensor have been built to validate the direct transfer of data from chip to chip and to read out the module via one chip only. Novel interconnection technologies such (ACF, nanowires) have been investigated to build a compact module. A lightweight flex with 17um trace/spacing has been designed that will allow compact packaging with a direct attachment of the MALTA2 chip connection pads to the flex using these interconnection technologies. We will present the module concept studies as well as the first results from demonstrator modules.

Speaker: Julian Weick (Technische Universitaet Darmstadt (DE))

Julian_Weick:_low-mass_module_concepts_based_on_MALTA.pdf

Summary.pdf

10:00 → 10:30 Coffee break

10:30 → 11:15 Invited

Convener: Alex Kluge (CERN)

TWEPP-2022_UVVM.pptm

10:30 The Mechanics of Innovation

A short trip into the world of innovation, especially in the high-tech sector.

Why is innovation important, what are the drivers and why is it so often not the established players who innovate? Let’s have a look at different industries and discover common challenges …

---

Michael Hähnle attained his master’s degree followed by a doctoral degree at the Vienna University of Economics and Business Administration. He also holds a degree as an Engineer in Electronics and Telecommunications.

Michael has more than 25 years of international management experience in different types of organizations with a strong focus on innovation and technology – from major fundamental research institutions to technology startups, SMEs, large international technology corporations, and multinational technology consulting firms. He provides expertise in technology marketing, strategy development, business development, leadership, sales and the establishment and development of organizations.

Michael is now a Manager at INiTS, Vienna’s High Technology Incubator, supporting entrepreneurs with R&D-based business ideas and connecting them with investors who want to invest in early stage high technology startups or in more mature health technology startups.

Speaker: Michael Haehnle

11:20 → 12:20 ASIC

Conveners: Marcus Julian French (Science and Technology Facilities Council STFC (GB)), Ping Gui

11:20 TDC with Uncontrolled Delay Lines: Calibration Approaches and Precision Improvement Methods

The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two "snapshots" of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each cell in the delay line can be calibrated for the operating temperature and voltage. The two measurements can also be averaged to improve the TDC measurement precision. We will discuss various calibration approaches and present test results in this work.

Speaker: Jinyuan Wu (Fermi National Accelerator Lab. (US))

TDC_paper2022c.pdf

UncontrolDelayLineTDC2022b1.pptx

11:40 Bandgap Reference, Temperature Sensor and Low Drop-out Regulator Circuits for Monolithic Sensors in TPSCo 65nm ISC Technology

The TPSCo 65 nm ISC technology is under study in the framework of the CERN-EP on monolithic active pixel sensors (MAPS) for High Energy Physics (HEP) applications, and the ALICE ITS3 upgrade project, for which a wafer-scale stitched MAPS sensor is under development. This contribution presents designs and measurement results for Bandgap Reference (BGR) and Temperature Sensor (TS) prototypes needed for this large chip, but also more largely applicable. Simulation results of the design of Low Drop-out Regulator (LDO) to be submitted for the next prototyping run will also be discussed.

Speaker: Asli Yelkenci (Nikhef National institute for subatomic physics (NL))

BGR_TS_LDO_TWEPP22.pdf

12:00 Waveform Sampler: A 2.56GS/s 12-bit Time-Interleaved Pipelined-SAR Analog-to-Digital Converter (ADC) with on-chip Memory

We report the development of a Waveform Sampler (WS) including the design and measurement results. The WS is developed as part of the Endcap Timing Readout Chip (ETROC) for the CMS MTD Endcap Timing Layer (ETL) for the HL-LHC. One of the ETROC 16x16 pixels is equipped with the waveform sampler, to sample the pixel’s preamplifier output waveform at 2.56GS/s and convert it into digital domain. This is similar to using an oscilloscope to record the waveform except this is on chip. The reconstructed waveforms will be used for periodically LGAD signal monitoring purposes during the CMS ETL detector operation.

Speakers: Xianshan Wen, Ping Gui

TWEPP2022_WS_final.pptx

11:20 → 12:20 Production, Testing and Reliability

Conveners: Magnus Hansen (CERN), Francois Vasey (CERN)

11:20 RD53A pixel module assembly and testing experience

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown. A new silicon Inner Tracker (ITk) will contain five innermost pixel layers equipped with new sensors and readout electronics capable to improve the tracking performance, cope with the high particle multiplicity and work in a high luminosity environment. In order to standardize modules of the ITk, the idea of a common hybrid module was introduced. The common hybrid module assembly and testing techniques will be presented. The module construction, metrology and electrical testing results will be discussed.

Speaker: Alexey Petrukhin (Siegen University)

AP.pdf

11:40 Electrical performances of pre-productions staves for the ATLAS ITk Strip Detector Upgrade

The ATLAS experiment is currently preparing for an upgrade of the inner tracking detector for High-Luminosity LHC. The new tracker, ITk, employs an all-silicon detector with outer Strip layers. The building block of the ITk Strip barrel is the stave which consists of a low-mass support structure hosting the common electrical, optical and cooling services as well as 28 silicon modules. In this contribution, we outline the challenging aspects of the stave pre-production testing phase at Brookhaven National Laboratory. The electrical characterization of these staves, hosting the final design of both front-end electronics and ASICs, will be discussed in detail.

Speaker: Francesca Capocasa (Brandeis University (US))

TWEPP22_FC.pdf

12:00 Automated visual inspection system for ATLAS strip hybrids

A method of automating the visual inspection of ATLAS upgrade strip modules is shown. The visual inspection of the hybrids is a time consuming part of the quality control during module production. A method of detecting and classifying the SMD components on the hybrids using an object detection neural network was investigated. The results show that the amount of hybrids that needed to be check by a human operator was reduced to around 10$\%$ of the batch. This hugely reduced the amount of time needed for human inspection and did find real mistakes done during the production of the hybrids.

Speaker: Paul Dervan (University of Liverpool (GB))

TWEPP2022-Dervan.pdf

12:30 → 14:00 Lunch

14:00 → 15:00 Optoelectronics and Links

Conveners: Francois Vasey (CERN), Johan Alme (University of Bergen (NO))

14:00 GBT20, a 20.48 Gbps PAM4 Optical Transmitter Module for Particle Physics Experiments

We report a pluggable radiation-tolerant PAM4 optical transmitter module called GBT20 (Gigabit transmitter at 20 Gbps) for the high-energy physics experiments. The core of GBT20 is an ASIC GBS20. GBT20 uses an OSFP or firefly connector to input 16-bit data each at 1.28 Gbps. GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. A custom latch couples an optical fiber to the module. Preliminary test results indicate the module meets the design goal. Full test results will be presented in the workshop.

Speaker: Prof. Jingbo Ye (Southern Methodist University)

GBT20_final.pdf

GBT20_supp_doc_v3.pdf

14:20 System development of Silicon Photonics links for CERN Experiments and Accelerators

Future upgrades of the CERN Experiments and Accelerators require optical links capable of handling the large data volume generated in particle detectors and beam position (BPMs) sensors. Silicon Photonics optical transceivers are the best candidates to cope with the required data rate and radiation tolerance. We present the experimental characterization of Silicon optical modulators and Germanium photodiodes together with lab demonstration of optical transmitters and receivers based on CERN custom designed Silicon Photonics integrated circuits.

Speaker: Carmelo Scarcella (CERN)

certificate2022_scarcella.pdf

TWEPP_2022_Silicon_Photonics_Carmelo_Scarcella.pdf

TWEPP_2022_Silicon_Photonics_Carmelo_Scarcella.pptx

14:40 Versatile Link+ Transceiver Production

The Versatile Link+ project targeting the Phase 2 HL-LHC detector upgrades has entered the production phase. After several years of prototyping and a successful pre-series production, the industrialisation of the Versatile Link+ Transceiver (VTRx+) was completed in 2021 and the VTRx+ modules are now being manufactured by an industrial partner. We describe the extensive qualification effort that preceded the launch of the series production and the quality assurance procedures put in place to monitor the manufacturing quality. We summarise the experience of the first few production months and we present the plans for the rest of the production.

Speaker: Csaba Soos (CERN)

VLplus_TWEPP2022.pdf

14:00 → 15:00 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Ken Wyllie (CERN), Hucheng Chen (Brookhaven National Laboratory (US))

14:00 Design and Prototyping of the CMS Phase-2 Trigger And Timing Distribution System

The CMS detector will undergo an upgrade for Phase-2 of the LHC
program. The back-end electronics will be implemented as ATCA node
boards, connecting to the central systems via a custom `DTH' hub
board.

Instead of a traditional distribution tree, the CMS Phase-2 Trigger
and Timing Distribution System (TCDS) will use a configurable
switching network to connect multiple hardware `run controllers' to
the back-end electronics. This approach increases flexibility by
removing the need for recabling to enable different detector
groupings.

This paper describes the architecture of the TCDS, as well as the
progress made prototyping the DTH and DAQ-800 hardware.

Speaker: Jeroen Hegeman (CERN)

twepp2022.pdf

14:20 Complete design of maximally-automated self-driven control mechanism for a large scale electronics system and its implementation to the ATLAS Phase-II TGC system

Establishing a reliable and efficient method to control electronics system consisting of many boards is critical in the system design. Among unique requirements for the control in high energy physics experiments, we propose a maximally-automated and self-driven scheme for a system that exploits FPGAs, SPI flash memory devices, and high-speed fixed-latency optical links. We have implemented our ideas in the demonstration system of Phase-II ATLAS Thin Gap Chamber (TGC) system as the prototype for this new automated scheme. The method is widely applicable, and the knowledge and experience can be shared with other FPGA-based electronics systems.

Speaker: Takumi Aoki (University of Tokyo (JP))

aoki_20220922_twepp_v4.pdf

award2022_aoki.pdf

TWEPP_abstract_figures.pdf

14:40 Lessons learnt from the first vertical slice of the CMS Outer Tracker

A slim vertical slice of the CMS Outer Tracker has been assembled at the Tracker Integration Facility at CERN. It includes the final 2S and PS front-end hybrids with an optical link to the back-end ATCA system, comprising the Data, Trigger and Control (DTC), DAQ & Timing Hub (DTH) and Track Finder (TF). The performance of the system will be described, such as the real-world cooling limits of racks at the Tracker Integration Facility and the CMS Underground Service Cavern; robustness of 25G trigger optical links, readiness of firmware and the first measurements of some key metrics (e.g. latency).

Speaker: Giacomo Fedi (Imperial College (GB))

TWEPP2022_tracker.pdf

15:00 → 15:30 Coffee break

15:30 → 16:15 Invited

Convener: Francois Vasey (CERN)

TWEPP-2022_UVVM.pptm

15:30 TCLink: How much your clock phase can change between different runs?

The LHC phase-2 upgrades will pose unprecedent challenges in terms of timing stability to the clock delivered to thousands of nodes in an experiment. Slow phase variations could dominate the overall timing stability in a clock recovered from a high-speed optical link.
The TCLink is an integrated protocol agnostic FPGA core that can monitor and correct slow phase variations in high-speed bidirectional links. Phase-determinism (how much a clock phase changes after restarts) may play a significant role in the overall stability. In this paper we present typical phase-determinism values for TCLink implementations and potential novel architectures to improve this metric.

Speaker: Eduardo Brandao De Souza Mendes (CERN)

tclink_ebsm_22_09_2022.pptx

16:15 → 16:35 Optoelectronics and Links

Conveners: Francois Vasey (CERN), Johan Alme (University of Bergen (NO))

16:15 High Speed Radiation Tolerant Optical Links based on Coarse Wavelength Division Multiplexing

The upgrade of CERN’s accelerator complex requires improved beam instrumentation systems that will generate an increased volume of data to be transferred from the radiation areas to the back-end. A solution that increases the throughput of already deployed fibers consists in implementing the coarse wavelength division multiplexing (CWDM) technique where independent optical carriers at properly spaced wavelengths are multiplexed into a single fiber. In this paper we describe the CWDM Link project, which scope is to realize a high speed radiation tolerant optical link based on four CWDM channels, and we investigate the radiation resistance of commercial CWDM components.

Speaker: Leonardo Marcon (CERN)

High Speed Radiation Tolerant Optical Links based on Coarse Wavelength Division Multiplexing.docx

TWEPP22_LeonardoMarcon.pdf

TWEPP22_LeonardoMarcon.pptx

16:15 → 16:35 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Ken Wyllie (CERN), Hucheng Chen (Brookhaven National Laboratory (US))

16:15 Design and Performance Optimisation of the Hexaboards for CMS HGCAL On-Cassette Readout Electronics

We present the design and performance of the Hexaboard, a complex hexagonal multi-layer PCB equipped with multiple HGCROC ASICs to read out the signals from silicon pads with low noise and large dynamic range. The Hexaboards are glued to silicon sensors and connect to them via wire bonds through holes in the PCBs. The Hexaboard also connects to mezzanine boards for powering, data concentration and data transfer. More than 10 variants of the Hexaboard are required to cover the circular fiducial area of the CMS endcaps. Detailed performance measurements, and comparative PCB simulations using ANSYS SIWAVE, will be presented

Speaker: Mr Fakhri Alam Khan (Universite Libre de Bruxelles (BE))

Fakhri-TWEPP2022-Abstract.pdf

Fakhri-TWEPP2022-Summary.pdf

Hexaboard Design and Performance Optimization for Silicon region of HGCAL_TWEPP-2022.pdf

16:40 → 18:00 Thursday posters session

poster_locations_Thur.jpg

poster_plan_hall.jpg

poster_plan_lounge.jpg

16:40 A high performance and low-cost multipurpose Cosmic Ray Detector

Proof of concept of a 2-channel Data Acquisition system for Astroparticles detectors.
The astroparticle detector is a 1000Lts Water Cherenkov Detector plus 2 scintillating pads.
This detector allow to perform measurements of the Vertical Equivalent Muon that are used to improve the calibration factors.

Speaker: Dennis Cazar Ramirez (Universidad San Francisco de Quito (EC))

16:40 A 14 Gbps VCSEL Driving ASIC in 55 nm for NICA Multi-Purpose Detector Project

This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed. The test results show the wide-open 14 Gbps optical eye diagram with a measured RMS jitter of 2.7 ps and a peak-to-peak jitter of 17.4 ps, respectively.

Speakers: Cong Zhao, Di Guo (Central China Normal University)

Supporting document_VCSEL driver.pdf

16:40 A 65nm Dual Mode 1.25/7 GHz PLL with CML Line Driver for ALICE ITS3 and EIC Applications

This paper presents a dual frequency PLL designed to support data transmission in next generation particle physics detectors. The PLL is designed in a 65nm CMOS process and operates in two frequency modes 1.25GHz in the lower frequency mode and 7GHz in the higher frequency mode. A PRBS generator is integrated with the PLL to enable testing and the design occupies 0.110um2 of silicon space. The design is intended for use in the ALICE ITS3 upgrade, and the Electron Ion Collider. Here we report test results on the supporting LVDS receiver and CML line driver, which have already been tested.

Speakers: Soniya Mathew, Iain Sedgwick

TWEPP2022_diagrams.docx

16:40 A Dedicated and Versatile System for Testing the Radiation Hardness of Various Integrated Circuits

This work presents a versatile system that is dedicated for the testing of various integrated circuits in radiation (e.g., FPGAs, ASICs). This system allows to power the device under test (DUT), and to monitor and read out in real time various parameters: power consumption (100 µV and 100 µA resolution), and various operational parameters. The system has built-in features to detect and test for SELs, SEUs and to monitor the DUT for TID and annealing phenomena. A graphical user interface allows the user to connect to the test bench through TCP/IP from a safe zone, and to record measurements data.

Speaker: Dr Vlad-Mihai Placinta (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO))

16:40 A four-channel front-end readout ASIC for high hit rate gas detector

The High-density High-precision High-speed Front-End Electronic (HFEE) is widely used in the high hit rate gas detectors. The design and characterization of a HFEE prototype is presented in this paper. The prototype chip is composed of four channels and each channel consists of a charge-sensitive preamplifier, a pole-zero cancellation circuit, a S-K filter and a gain amplifier. The simulations show that the equivalent noise charge is about 779e- + 3.592/pF, the non-linearity is less than 1% and the hit rate is up to 10MHz. The test work is being prepared and the test results will be presented in the conference.

Speakers: Yuxin Qiao, Chaosong Gao (Central China Normal University)

A four-channel front-end readout ASIC for high hit rate gas detector.pdf

Supporting document A four-channel front-end readout ASIC for high hit rate gas detector.pdf

16:40 A radiation hard bandgap voltage reference for the ARCADIA project

This work presents the design and characterization of a radiation hard bandgap reference circuit fabricated in a 110nm CMOS technology for the Main Demonstrator chip of the ARCADIA project. The design, based on a current-mode approach in order to be able to output a smaller than 1.2V reference voltage, employs diode-connected MOSFETs instead of BJTs to enhance the radiation hardness and a second amplifier to improve the current mirror of the output branch and therefore the line regulation of the circuit. This paper describes the features of the circuit and its measured results.

Speaker: Gianluca Traversi (Pavia University and INFN (IT))

summary TWEPP 2022.pdf

16:40 A Readout System for Monolithic Pixel Sensor prototypes towards the ITS3 upgrade of the ALICE Inner Tracking System

The ITS 3 project within the ALICE Experiment is developing an innovative vertex tracker to be installed during the Long Shutdown 3 of the LHC. Based on a commercial 65 nm CMOS imaging technology, it consists of cylindrical sensors that can be installed as close as 18 mm to the interaction point.

In order to validate the technology, test chips were produced in a first submission named MLR1. This contribution will describe the development of a test system for some prototypes of MLR1, namely Analogue and Digital Pixel Test Structures (APTS, DPTS) and pixel matrices with rolling shutter readout (CE65).

Speaker: Valerio Sarritzu (Universita e INFN, Cagliari (IT))

fig1.png

fig2.png

16:40 Analog performance of the CROC-V1 pixel readout chip for the CMS Phase-2 Tracker Upgrade

The CROC-V1 readout front-end (FE) chip was designed by the RD53 collaboration for the CMS Phase-2 Inner Tracker Upgrade. It is designed to cope with the extreme radiation and hit rates of the HL-LHC and it is based on the 65 nm CMOS technology and a novel analog FE design featuring linear charge to Time-over-Threshold (ToT) conversion. In this contribution, the characterization measurements of the analog part of the chip are presented with a special focus on the linear analog FE, including Total Ionizing Dose (TID) radiation damage studies.

Speaker: Alkiviadis Papadopoulos (University of Patras (GR))

16:40 ATLAS LAr Calorimeter Commissioning for LHC Run-3

To cope with an increase of luminosity at Run-3 of the LHC, a new trigger readout path has been installed to the Liquid Argon Calorimeters.

More than 1500 boards of the legacy system were refurbished and re-installed, 124 new on-detector boards equipped with large FPGAs were added to digitize the calorimeter trigger signals, and all the monitoring and control infrastructure is being adapted and commissioned.

This contribution will present the challenges of the installation, the commissioning and the milestones still to be completed towards the full operation of both the legacy and the new readout paths for the LHC Run-3.

Speaker: Jiaqi Zang (University of Tokyo (JP))

TWEPP2022_ATLAS_LAr_commissioning.pdf

16:40 BigRock, a Fast Timing Front End for Future Pixels in a 28 nm CMOS Process

A high-speed, low-power analog front end (AFE) utilizing a current-mode signal path has been designed for 4D tracking applications where precision time resolution of order 50 ps is a requirement. The preamplifier concept is based on a prior art current-feedback CMOS topology [1]. The power consumption of the AFE is 6 uA at 0.9 V process voltage. An on-chip test bench comprised of a variable injection circuit and high-resolution TDC, synchronized by a 1 GHz system clock, is used to measure the AFE timing resolution. The design is fabricated as a 32-channel prototype ASIC, and includes high-speed custom IO IPs.

Speaker: Zhicai Zhang (Lawrence Berkeley National Lab. (US))

16:40 bPOL48V, rPOL48V and linPOL48V: 48V-input-rated rad-hard POL converters for HEP experiments

Three new Point-of-Load (POL) converters, suitable for the High Luminosity – Large Hadron Collider (HL-LHC) experiments and for space/avionic applications, are under development. The two DCDC converters, called bPOL48V and rPOL48V, allow a significant improvement in the power delivery requirements as they can provide higher power at an increased input voltage of 48V, compared to existing solutions. The linear regulator, called linPOL48V, can supply up to 200mA with programmable output voltage, from up to 48V input. This work addresses the characterization of bPOL48V and linPOL48V, which are approaching production readiness, and the first results obtained on the rPOL48V prototype.

Speaker: Pablo Daniel Antoszczuk (CERN)

TWEPP2022 - Abstract_summary FV.docx

TWEPP2022 - Poster - 48V power conversion.pdf

16:40 Characterisation of the first digital modules with RD53B-CMS readout chips for the Phase-2 Upgrade of the CMS Inner Tracker

To cope with the challenges posed by the High-Luminosity LHC, the CMS experiment will feature a new silicon tracker. The modules for the inner tracker are hybrid silicon pixel modules based on a new readout ASIC, developed by the RD53 Collaboration, capable of sustaining higher hit rates and radiation levels and enabling the use of serial-powering chains. The qualification of the latest version of the RD53 chips (RD53B) is underway, and it will lead to the final version of the readout ASIC for CMS. This contribution will present results of tests on the first digital modules featuring the RD53B-CMS chip.

Speaker: Marino Missiroli (Paul Scherrer Institut, Universität Zürich (CH))

16:40 CMS tracker phase-2 upgrade module noise and mitigation

The CMS tracker phase-2 upgrade modules are required to reach noise levels close to the ones expected from the analog front-end attached to an ideal pixel/strip. Module prototypes, featuring the latest and final prototype hybrids before the production, showed noise that was higher than the expected which could pose a problem in terms of achieving the hit efficiency target. Investigations that followed, lead to an unexpected failure mode which is modeled in order to guide mitigation tweaks for the production designs. Knowledge acquired from the investigations along with the noise mitigation design changes implemented on the production hybrids are presented.

Speaker: Angelos Zografos (CERN)

Module_noise&mitigation_vf.pdf

16:40 Data-Driven Design of the Belle II Track Segment Finder

The Belle II experiment relies on a level-1 trigger system to reduce background and preselect events of interest for particle physics. The Central Drift Chamber is the main track detector which makes its trigger system important for online track reconstruction. To improve its hit efficiency a new extension of the track segment finder for low angel tracks is designed. By combining hardware and software development flows, an automated data-driven pipeline is created and three different-sized hardware concepts are implemented. The operation point is adjustable to balance hit efficiency against hit purity in the trigger system.

Speaker: Marc Neu (KIT)

16:40 Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65nm CMOS imaging technology

The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65nm ISC process in the framework of the CERN-EP R\&D on monolithic sensors and the ALICE ITS3 upgrade.
It features a 32x32 binary pixel matrix at 15 $\mu m$ pitch with event-driven readout, based on GHz range time-encoded digital signals including Time-Over-Threshold.
The chip proved fully functional and efficient in test beam allowing early verification of the complete sensor to readout chain.
The focus is on the design and in particular the digital readout and its perspectives with some supporting results.

Speaker: Leonardo Cecconi (CERN)

DPTS_poster_TWEPP22.pdf

16:40 Exploring FPGA in-storage computing for Supernova Burst detection in LArTPCs

Latency and computational resources are key constraints for high bandwidth, low latency trigger systems. In these systems, even if a GPU/FPGA is used to accelerate computation, transferring data between components is still a costly operation for the host. In this work, we study a computational storage system employing FPGAs to detect supernova neutrino bursts, with a particular focus on LArTPC experiments. The computational storage system filters on interesting signals via machine learning wire reconstruction deployed on an FPGA and reduces data volume before storing in real-time. This workflow is applicable in other analysis/trigger applications including cosmology and particle physics experiments.

Speaker: Jovan Mitrevski (Fermi National Accelerator Lab. (US))

TWEPP_IEEE NSS Poster - Exploring FPGA in-storage computing for Supernova Burst detection in LArTPCs v2.pdf

16:40 Fast prototyping of Front End ASICS and validation of associated DAQ with a Cadence Protium platform.

ASICs designed for HEP embed always more digital components and require complex and critical verifications. Prototyping enables implementations of digital part of ASIC in programmable components such as FPGA. Interactions with external devices such as DAQ, micro-controller or other FPGA are then possible. Debugging of internal firmware or complex stimuli becomes easier and faster than time-consuming simulations.
Cadence Protium is an FPGA based solution that allows ASIC designers to easily and automatically prototype the RTL code of their ASIC. This platform and its use for the validation of several ASIC DAQs and slow-controls developed at IPHC will be presented.

Speaker: Mr Grégory Bertolone (Université de Strasbourg,CNRS,IPHC)

Twepp22_Bertolone.pdf

16:40 Fast Tracking Read-Out Electronics for ATLAS sMDT Detectors in 65nm CMOS

This paper presents 4-channel readout electronics for small-diameter Muon-Drift-Tube (sMDT) detectors. Design is optimized largely for higher detection rate of events at High Luminosity of LHC and thus significantly reducing the impact of pile-up events and eliminating use of long deadtime logic. Analog chain of the design consists of Charge-Sensitive-Preamplifier, to convert input charge into voltage pulse, followed by a shaper. Novelty of design is in fast resetting all stages just after the charge information is extracted. Design operates with a 5 –100 fC input charge range. The design is realized in 65nm technology and operated is from 1.2V supply.

Speaker: Syed Adeel Ali Shah

Fast_Tracking_Readout_65nm.pdf

16:40 FELIX: the new ATLAS readout system from Run 3 to High Luminosity LHC

The Front-End Link eXchange (FELIX) system is a new ATLAS DAQ component designed to meet the evolving needs of detector readout into the High-Luminosity LHC era. FELIX acts as the interface between the data acquisition; detector and trigger timing and systems; and new or updated trigger and detector front-end electronics. FELIX routes data between custom serial links from front-end electronics to data collection and processing components via a commodity switched network. This presentation covers the design of FELIX and its evolution for High-Luminosity LHC, plus commissioning activities ahead of Run 3.

Speaker: Marius Wensing (Bergische Universitaet Wuppertal (DE))

certificateTwepp2022_bergamin.pdf

FELIX_Figures_TWEPP2022.pdf

TWEPP_Poster_FELIX.pdf

16:40 Future developments of radiation tolerant sensors based on the MALTA architecture

The planned MALTA3 DMAPS designed in the standard TowerJazz 180 nm Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x1015 MeV neq/cm2. The effectiveness of these changes have been demonstrated in recent measurements with a small-scale mini-MALTA demonstrator chip. Proposed changes in the periphery of the MALTA3 sensor are listed and discussed, with an added focus on timing performance improvements (<1ns resolution) as well as research of the overall sensor architecture.

Speaker: Mr Dominik Dobrijevic (University of Zagreb (HR))

Dobrijevic_TWEPP_final.pdf

Future developments of radiation tolerant sensors based on the MALTA architecture.pdf

16:40 High Voltage consolidation of the temperature measurement channels of the LHC superconducting current leads

Recurrent dielectric breakdowns on the cryogenics instrumentation during the CERN LHC Electrical Quality Assurance (ELQA) campaigns led to an investigation of their root causes. During the CERN Long Shutdown 2 (LS2), several weaknesses were identified like floating wires or cable screens, cabling non-conformities, connector assembly issues, and weakness of the electronic conditioning cards. The paper presents the cabling layout from the sensor till the acquisition cards and the actions undertaken to increase the robustness against dielectric ruptures. These actions include rebuild of the cabling and connectors using a laser stripping machine, new wiring patterns and upgrades on the electronic cards.

Speaker: Nikolaos Trikoupis (CERN)

16:40 Influence of High-Frequency Magnetic Fields on Noise Behavior of CMS 2S Module Prototypes

For the CMS tracker Phase-2 upgrade new modules with silicon strip sensors are being developed. Each module features a Service Hybrid (SEH) responsible for communication with the tracker back-end and power distribution to the module components. Here, a two stage DC-DC conversion scheme is used for the supply of low voltage. For modules using the latest generation of SEHs an increase in module noise has been observed. A setup for inducing radiative noise with external magnetic fields that are frequency and location dependent will be presented. Resulting measurements suggest that radiative sources are not responsible for the observed noise increase.

Speaker: Nicolas Maximilian Roewert (RWTH Aachen University (DE))

16:40 LAPPD operation using FASTIC and PETSYS ASICs

Single photon sensitive detectors used in high energy physics are required to cover very large areas, with a strong demand for an ever finer imaging capability. We are evaluating the LAPPD as a possible candidate for future Cherenkov ring imaging detectors, performing tests on a generation I device, which is capacitively coupled to a custom designed anode back plane, consisting of various pixels and strips varying in size, and allows for connecting various readout systems, such as standard laboratory equipment, as well as the ToFPET2 ASIC from Petsys and the FASTIC ASIC developed by UB and CERN.

Speaker: Andrej Seljak

16:40 LTDB, the Lar Trigger Digitizer Board: from design to mass production for ATLAS Liquid Argon Calorimeters Phase-1 Upgrade

To increase granularity, resolution, and provide longitudinal shower shape information from the ATLAS LAr calorimeters to its level-1 trigger processor, a new radiation-hard board has been designed during the phase-1 upgrade. This Lar Trigger Digitizer Board adapts and digitizes up to 320 detector inputs using custom ADCs and sends the serialized data through 200Gbps optical links. The run control of the board is implemented through five bidirectional GBT links. 150 boards have been produced and validated with an elaborated test-bench based on a complex custom-built signal injector and the FELIX DAQ. The board architecture and the test-bench organization are presented.

Speaker: Aude Marie Grabas (Université Paris-Saclay (FR))

twepp22_poster_v1.pdf

16:40 Maintaining data integrity in a cryogenic SoC ASIC driving 25 m cable at 160K and 87K with gigabit data rates

The ASICs for charge readout of the DUNE and nEXO experiments will operate under noble liquid environments and will transmit data over long cables (up to 25 m). We have designed a custom LVDS transmitter to cope with the cable insertion loss and maintain data integrity. The transmitter features a tunable pre-emphasis circuit and bias current, which allows us to drive different cable lengths at cryogenic temperatures. We will present the characterization and modeling of the cable insertion loss, the design of the custom LVDS driver, and the comparison of eye diagrams at various frequencies and temperatures.

Speaker: Aseem Gupta

LVDS_Cable_Loss.jpg

SLAC_CRYO_TX_TWEPP_2022.pdf

16:40 Modern high-availability multi-stage power distribution system for the CMS phase-2 upgrade.

The operation of CMS at the HL-LHC requires an upgrade of the readout electronics. These new modern micro-electronics require power at precise voltages between 1.2V and 2.5V. We will deliver this power using a 3-stage system, comprising AC-DC conversion to 400VDC followed by radiation-tolerant 12V DC-DC power converters feeding radiation-hard point-of-load DC-DC converter. We have studied an industrial 400V AC-DC conversion system, featuring hot-swappable 3kW power modules, stackable up to ~1MW system depending on the application needs. Our tests demonstrated that the system complied with our requirements, most notably in terms of easy maintainability, high availability and power quality.

Speaker: Krzysztof Stachon (ETH Zurich (CH))

TWEPP 2022 - Supplementary materials.pdf

16:40 MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

Abstract:
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs of voltages or temperatures to an lpGBT ADC channel through a 6-bit decoder. A total of 92x3 dies were fabricated in two batches by the TSMC 130 nm CMOS technology. All of them passed the quality assurance test after bare dies were wire-bonded to PCBs or being packaged chips. Negligible degradation was observed in a 16-day aging test at 85℃.

Speaker: Mr Zifeng Xu (Nanjing University (CN))

TWEPP2022_draftv4.pdf

TWEPP_abstract-An Optional File for MUX64(final)(1).pdf

16:40 Pre-Production Testing of the HCCStar at Penn for the ATLAS ITk Detector

The high-luminosity LHC requires a complete overhaul of the ATLAS inner tracker subsystem, including a new silicon-strip charged-particle tracking detector. The HCCStar (Hybrid Controller Chip) is one of three new ASICs for this subsystem. As the interface to multiple binary readout ASICs for the strip detector, the HCCStar buffers and forwards controls signals and trigger and readout requests to them, and serializes their output at 640 MHz. All HCCStars undergo a suite of tests to verify their analog and digital functionality, and large statistics of performance with various operational parameters are collected.

Speaker: Bobby McGovern (University of Pennsylvania (US))

rmcgov-TWEPP-Poster.pdf

16:40 Qualification tests of the PASTTREC readout ASIC for straw tube detectors

PASTTREC is an 8-channel readout ASIC for the Straw Tube Tracker (STT) and the Forward Tracker (FT) detectors in the PANDA and for the Straw Tracking System (STS) in the HADES experiments, both at the FAIR facility. Since more than 1500 ASICs were produced for both experiments, efficient qualification tests are required. For this purpose, the multi-chip test setup and dedicated verification procedures were developed. In this contribution, the results for the first batch of 280 PASTTRECs, showing a yield of approximately 94%, with a particular emphasis on the process-related spread of key ASIC parameters, will be discussed.

Speaker: Aleksandra Molenda (AGH University of Science and Technology (PL))

2022_TWEPP_Bergen_PASTTREC_poster.pdf

16:40 Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard

The new electronics of the ATLAS TileCal for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and and mitigates and radiation damage by means of a double-redundant scheme, Triple Mode Redundancy, Xilinx Soft Error Mitigation IP, CRC/FEC for link data transfer, and SEL protection circuitries. We present an updated summary of the TID, NIEL and SEE qualification tests, and performance studies of the Daughterboard revision 6 design.

Speaker: Eduardo Valdes Santurio (Stockholm University (SE))

Radiation_studies_performed_on_the_High_Luminosity_ATLAS_TileCal_link_Daughterboard.pdf

twepp_poster_v3.pdf

16:40 Radiation tolerance studies of the HV-Mux GaN FETs for the HL-LHC ATLAS ITk Strip Detector

The ITk Strip is a silicon-strip charged-particle detector that is going to be installed in the ATLAS experiment for the HL-LHC. GaNFETs are radiation-tolerant transistors that permit switching off high voltage to malfunctioning sensors. To ensure the reliability of the GaNFETs in the high radiation environment expected for the ITk Strip, a sample of the transistors were exposed to gamma and heavy ion radiation. The GaNFETs were characterized pre- and post- irradiation, and their state was monitored during irradiation. We will report on the results of these irradiations.

Speaker: Luis Felipe Gutierrez Zagazeta (University of Pennsylvania (US))

GaNFETs-TWEPP2022-Updated.pdf

16:40 RAFAEL : A Clock and Data Fan-Out ASIC for CMS HL-LHC Upgrades

In order to achieve tens-of-ps particles time-tagging performance required at HL-LHC, the CMS clock tree is being upgraded. A radiation-hard fan-out ASIC, named RAFAEL, was developed to distribute the clock and the data to the frontend ASICs of the CMS detectors that require precision timing, including BTL and HGCAL. Its main constraint is a low additive jitter, less than 4 ps RMS, even after 300 Mrad and $5\cdot10^{16}$ n$_{eq}$ 1 MeV/cm$^2$ irradiation. The chip architecture is presented along with its performance in the substantially different use cases proper for BTL and HGCAL.

Speaker: Fabrice Guilloux (Université Paris-Saclay (FR))

RAFAEL_Poster_V4.pdf

Summary_TWEPP22_RAFAEL_v2.docx

Summary_TWEPP22_RAFAEL_v2.pdf

16:40 Readout Electronics for High Intensity Range Particle Beam Monitoring

For readout electronics capable of exploiting the characteristics of 4H−SiC, we are in testing and optimization phase of a single channel circuit to continuously detect single particles up to GHz rates, including statistical pile-up detection by ToT measurements of shaped pulse signals.
Furthermore, we are evaluating an IC with 128 input channels, originally intended for X-ray imaging, which individually integrates the DC coupled electric currents delivered by sensor strips over some time into capacitors in order to monitor the particle beam at even higher luminosities. Shown are first results of a test beam at MedAustron.

Speaker: Richard Thalmeier (Austrian Academy of Sciences (AT))

singlechannel_block_diagram.png

16:40 RISC-V processor evaluation with Cadence Protium platform

RISC-V is an open standard instruction set architecture with a large community that gives access to many resources (such as architecture, operating systems, tool chains, ...). The use of such a processor could be interesting in several ways for the HEP community. For example, it could be used to have a versatile supervisor of complex chips. The purpose of this presentation is to evaluate the development of RISC-V using the Protium prototyping platform from Cadence. Protium is an FPGA board based solution for prototyping digital ASICs without any RTL modifications.

Speaker: Frederic Morel (Centre National de la Recherche Scientifique (FR))

poster_morel_4904756.pdf

16:40 Second generation Monitoring of Pixel System (MOPS) chip for the Detector Control System (DCS) of the ATLAS ITk Pixel Detector

The Monitoring of Pixel System (MOPSv2) chip is an Application Specific Integrated Circuit (ASIC) foreseen to provide the temperature and the voltage monitoring data of individual front-end detector modules to the Detector Control System (DCS) of the ATLAS ITk Detector.The chip is required to be radiation hard up to an ionizing dose of 500 Mrad, immune to Single Event Upsets (SEUs) and work reliably at high operating temperatures of up to 40 degrees. In this talk, the functionality / performance of the second version of the chip will be discussed, and also results
from the irradiation campaigns will be presented.

Speaker: Rizwan Ahmad (Bergische Universitaet Wuppertal (DE))

Poster_twepp_2022.pdf

16:40 SEU injection framework for radiation-tolerant ASICs, a formal verification approach

Single Event Upsets (SEUs) represent a major challenge for digital electronics operated in a radiation environment.
Triple Modular Redundancy (TMR) is one of the most popular approaches to increase digital electronics resilience to SEUs.
Simulation is the most used approach for verifying the correct triplication of the designs.
This contribution describes a novel approach for verifying the triplication.
A formal verification tool is used, removing the need for a complete functional verification framework for the SEU injections in the design.
The approach allows finding bugs earlier in the design phase hence reducing the development and debug time.

Speaker: Matteo Lupi (CERN)

twepp2022_mlupi.pdf

16:40 Status of the Level-0 ATLAS Barrel Muon Trigger for High-Luminosity LHC

The ATLAS level-0 barrel muon trigger for High-Luminosity LHC will use data from RPC and MDT muon detectors and from the Tile Calorimeter. RPC hit data will be collected by on-detector Data Transmitter and Collector (DCT) boards and will be sent off-detector to the Sector Logic (SL) boards. Within a latency of 390 ns the SL boards should provide muon pre-candidates to the MDT trigger processor for an improved momentum measurement. This contribution presents the design of the system and results of recent tests of DCT and SL prototypes and firmware.

Speaker: Federico Morodei (Sapienza Universita e INFN, Roma I (IT))

poster_TWEPP_2022.pdf

16:40 STRV – A radiation hard RISC-V microprocessor for high-energy physics application

Currently microprocessors are precluded from the use in several high-energy physics applications due to the harsh radiation present. The STRV-R1 (SEU-tolerant-RISC-V) RSIC-V microprocessor aims to overcome this limitation and replace the custom digital control logic found in current ASICs. A triple modular redundancy (TMR) based protection scheme is applied to protect the RISC-V microprocessor core and other system components like the SRAM against radiation induced soft errors. The implementation has been done in a 65nm CMOS technology.
The radiation hard architecture of the RISC-V microprocessor is discussed and initial measurements of the first silicon are presented.

Speaker: Alexander Walsemann (Fachhochschule Dortmund Univ. of Applied Sciences and Arts (DE))

strv_a0_twepp_2022.pdf

16:40 System Integration of ATLAS ITK Pixel DCS ASICs

During the ATLAS phase II upgrade, the tracking system of the ATLAS exper-
iment will be replaced by an all-silicon detector called the ITk (Inner Tracker)
with a pixel detector as the most inner part.
The control and monitoring data of the new system will be aggregated from an
on-detector ASIC called MOPS (Monitoring Of Pixel System) and sent to the
DCS using a new interface called MOPS-HUB.
The hardware components of the MOPS-HUB, firmware specifications for the
FPGA of MOPS-HUB and its integration plan will be presented. In addition,
an irradiation plan for the new system will be introduced.

Speaker: Ahmed Qamesh (Bergische Universitaet Wuppertal (DE))

16:40 System tests of the ATLAS ITk planar and 3D pixel modules

In order to validate the design of the new all-silicon Inner Tracker (ITk) for ATLAS for the HL-LHC, a series of system tests has been performed, to assess the performance of prototype planar and 3D pixel modules arranged into serial power chains mounted on to realistic mechanical structures. In this report, the prototype loaded local supports and test infrastructure is described and the key results presented.

Speaker: Roman Mueller (Universitaet Bern (CH))

TWEPP_poster.pdf

16:40 Testing of the HCC and AMAC functionality and radiation tolerance for the HL-LHC ATLAS ITk Strip Detector

A new silicon-strip charged-particle detector (ITk Strip) is a major subdetector of the future upgrade of the ATLAS experiment for the HL-LHC. The HCC and AMAC chip are radiation-tolerant ASICs that contribute to the front-end readout, monitoring and control of the ITk Strip subdetector. Comprehensive probe station testing procedures have been developed to guarantee the reliability of each ASIC before installation. In addition, to ensure the operation of the HCC and AMAC under a radiation heavy environment, gamma, heavy ions and proton irradiation campaigns have been successfully conducted.

Speaker: Luis Felipe Gutierrez Zagazeta (University of Pennsylvania (US))

HCCAMACTestingRadiation-TWEPP2022-Poster-Updated.pdf

16:40 The LHCb Vertex Locator fast calibration

The LHCb Experiment was upgraded to a trigger-less system reading out the full detector at 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) is a hybrid pixel detector read out by the "VeloPix" ASIC with on-chip zero-suppression. This talk describes a novel way of calibrating the VELO detector based on a dedicated firmware, implemented in the control and data acquisition back-end boards of the detector.

Speaker: Antonio Fernandez Prieto (Instituto Galego de Física de Altas Enerxías (IGFAE) Universidade de Santiago de Compostela (ES))

Abstract_twepp22_velo.pdf

TWEPP2022-The LHCb vertex locator fast calibration.pdf

16:40 The NA62 liquid krypton electromagnetic calorimeter fast readout implementation, commissioning and data taking performance

The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. In this work we present the novel implementation of the readout data collection and forwarding system in the multiple layers of the calorimetric trigger structure. We will also present the commissioning of the system and the performance evaluation on current data taking.

Speaker: Roberto Ammendola (INFN e Universita Roma Tor Vergata (IT))

16:40 The new readout system of the ALICE Zero Degree Calorimeters in LHC Run 3

The Zero Degree Calorimeters were designed to provide the measurement of the event geometry and the luminosity in heavy ion operation. The readout system was redesigned in order to operate in continuous mode without dead time at 5 MHz event rate. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of about 1 GSps, assembled on an FPGA Mezzanine Card. The signals produced by the 26 ZDC channels are digitized, and the samples are processed through an FPGA to extract information as timing, baseline average estimation and luminosity measurements.

Speaker: Gianni Mazza (Universita e INFN Torino (IT))

SummaryTWEPP_v5.pdf

16:40 The Optosystem: validation and testing of the high-speed optical-to-electrical conversion system for the readout of the ATLAS ITk Pixel upgrade

After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs optical-to-electrical conversion of signals from the pixel modules. We present recent results related to the performance of the data transmission chain pivoted on the Optoboards and to the design, testing and production of the Optopanels.

Speakers: Mr Daniele Dal Santo (Universität Bern), Francisca Munoz Sanchez (University of Manchester (GB))

TWEPP_poster_Optosystem.pdf

16:40 Thermal and Humidity Monitoring in "Cold" Detector Control and Safety System

As high readout channel density and compact design become the norm for HEP detectors so is operation at temperatures below the experimental site dewpoint. This increases the importance of humidity and temperature monitoring systems that are also adapted to the detector environment. In what follows we describe the systems we developed targeting compactness, cost and integration to our DCS/DSS systems. The proposed temperature monitoring system is aimed at thousands of RTDs with low space and price requirements. For humidity measurements, we have identified a potential sensing element and designed conditioning electronics capable of nulling the capacitance of the long cables.

Speaker: Amar Kapic (University of Montenegro (ME))

16:40 Thermal Annealing in Silicon Photonics Ring Modulators

Silicon Photonics is a promising technology for future HEP experiments and upgrades. Such experiments and upgrades will require high levels of radiation tolerance and Silicon Photonics Modulators have already been shown to be very radiation tolerant when exposed to high levels of TID under certain conditions. We demonstrate for the first time that changing the temperature of Ring Modulators during or after the irradiation can improve their performance.

Speaker: Milana Lalovic (University of Belgrade (RS))

M.Lalovic_TWEPP2022_summary.docx

TWEPP2022_poster_M.Lalovic_final.pdf

16:40 Timing and Synchronization of the DUNE Neutrino Experiment

Synchronizing the different parts of a Particle Physics detector is an essential part of its operation. In the DUNE liquid argon neutrino detector timing information is transmitted to the readout systems and time-stamped data is sent to the DAQ.

We describe the DUNE timing system, which uses Duty Cycle Shift Keying with 8b10b encoding and a simple message protocol. The system is designed to allow simple implementation in the readout system timing endpoints.

Speaker: David Cussans (University of Bristol (GB))

dune_timing_system_twepp2022_cussans_v0-2.pdf

18:00 → 19:00 Scientific Committee meeting

Friday, 23 September

09:00 → 10:00 Production, Testing and Reliability

Conveners: Francois Vasey (CERN), Magnus Hansen (CERN)

09:00 Radiation hard TwinAx for ATLAS ITk pixel electrical data transmission

The high radiation dose and the cold environment at the HL-LHC pixel detector regions presents serious challenges for the survival of optical components. Radiation hard twinax cables are developed for the ATLAS ITk pixel data transmission within the pixel detector volume for up to 6m before transitioning to optical links at larger radius where radiation dose is reduced to acceptable level for optical components. We will present the design, qualification and industrialization process of the ATLAS ITk pixel electrical links using such twinax cables.

Speaker: Mr Andrew Young (SLAC National Accelerator Laboratory (US))

Figures_DataTrans-TwinAx-TWEPP-2022.pdf

TWEEP_22.pdf

TWEEP_22.pptx

09:20 Current status of the End-of-Substructure (EoS) card project for the ATLAS Strip Tracker Upgrade using final ASICs

The building blocks of the ATLAS Strip Tracker for HL-LHC are modules that host silicon sensors and front-end electronics. The modules are mounted on carbon-fibre substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card on each substructure side connects up to 28 differential data lines at 640 Mbit/s to lpGBT and VL+ ASICs that provide data serialisation and 10 GBit/s optical data transmission to the off-detector systems respectively. We present the final EoS electronics design, integration aspects, and results from recent quality assurance tests with final lpGBTv1 and VL+ ASICs from CERN.

Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE))

TWEPP_2022.pdf

TWEPP_2022.pptx

09:40 Production and Testing of the Powerboard for ATLAS ITk Strip Barrel Modules

The upgrade of the ATLAS ITk strips detector for HL-LHC will employ a custom PCB (Powerboard) for on-module DC-DC conversion, HV switching, and monitoring. This contribution will present the production procedure and mass test system for 15,000 Powerboards. We will also present the challenges identified during prototyping and pre-production and the performance of the Powerboard with the latest DCDC converter (bPOL12V) and controlling ASIC (AMACStar). Reliability tests of various components on Powerboards were also performed and results will be presented.

Speaker: Zhicai Zhang (Lawrence Berkeley National Lab. (US))

TWEPP2022_Zhicai.pdf

09:00 → 10:00 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Hucheng Chen (Brookhaven National Laboratory (US)), Ken Wyllie (CERN)

09:00 The CMS Muon Drift Tubes HL-LHC Upgrade Demonstrator at Run 3 Start

The electronic system of the CMS Drift Tubes (DT) chambers will be replaced to operate during High Luminosity (HL-LHC). The upgraded architecture ships all signals to the backend, where complex logic will be performed with a precision matching the maximum chamber resolution. A demonstrator has been installed during Long Shutdown 2 (LS2) in one of the sixty sectors of the detector. Over LS2 we have integrated this system in CMS operations environment and tested its stability over extended cosmics data-taking campaigns, also with the magnetic field on. The time synchronization achieved and early performance in collisions will be presented.

Speaker: Ignacio Redondo Fernandez (Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))

CMSDT_Slice_Test_TWEPP22_redondo.pdf

DeltaTimeQ_MB4.png

09:20 Commissioning and running experience with the CMS GE1/1 system

We present the commissioning and the running experience of the CMS GE1/1 system which has been installed in CMS in October 2020. Since then, GE1/1 has been commissioned and it is now ready for LHC Run-3. The GE1/1 detectors are read-out by the VFAT3 chip which communicates with the microTCA backend through the versatile link. Each detector has 24 VFAT3s, 3 GBTx, 3 VTRx, 2 VTTx, and a Virtex-6 FPGA. All powered by 10 FEAST DCDC converters. We will report on the GE1/1 electronics performance, stability, and the experience acquired over 2 years of commissioning.

Speaker: Laurent Pétré (Universite Libre de Bruxelles (BE))

LPetre-Commissioning-CMS-GE11-System-20220922-v4.pdf

09:40 TEPX as a high-precision luminosity detector for CMS at the HL-LHC

The CMS BRIL project upgrades its instrumentation for the Phase-2 detector to provide high-precision bunch-by-bunch luminosity and beam-induced background measurements. A part of the CMS Inner Tracker - the Tracker Endcap Pixel Detector (TEPX) - will allocate a fraction of the read-out bandwidth for luminometry. In order to be used for luminosity measurement, TEPX will require a dedicated trigger distribution system, while the raw data will be processed by a real-time on-FPGA pixel cluster counting algorithm. The most recent status of both developments will be presented.

Speaker: Mykyta Haranko (CERN)

haranko_twepp_2022_09_23.pdf

10:00 → 10:30 Coffee break

10:30 → 11:15 Invited: ECFA roadmap implementation for future R&D in electronics

Convener: Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))

TWEPP-2022_UVVM.pptm

10:30 Invited - ECFA roadmap implementation for future R&D in electronics

Abstract
This presentation will review the main recommendations of the 2021 ECFA detector R&D roadmap. It will highlight their potential impact on long-term R&D for electronics and outline the envisaged implementation scenario.

Biography
Francois Vasey holds an electronics engineering degree from ETH-Zurich and a PhD degree in optoelectronics from EPF-Lausanne. He joined CERN in 1994 to develop radiation resistant optical links for LHC experiments.
Since 2018, Francois is the head of the Electronic Systems for Experiments group at CERN (EP-ESE). He is currently leading the Versatile Link Plus project for the phase II upgrades of the HL-LHC experiments and is the electronics coordinator of the CMS Outer Tracker upgrade project.

Speaker: Francois Vasey (CERN)

ECFA Roadmap Implementation for future R&D in Electronics.pdf

11:20 → 12:00 Production, Testing and Reliability

Conveners: Magnus Hansen (CERN), Francois Vasey (CERN)

11:20 Wafer level test of the readout chip of the CMS Inner Tracker for HL-LHC

As part of the CMS Tracker upgrade for High-Luminosity LHC, the Inner Tracker community is developing an automated test system for the qualification of the front-end chip (CROC) before the wafer is sent to the company for dicing and hybridization. The procedure takes approximately one day for each wafer to be tested, thus allowing to fully verify the functionalities of all the chips in the tight timeline (18 months) allocated to the project. The talk will describe the test procedure and strategy, the setup and the results obtained on the first eigth wafers tested of the CROC prototype.

Speaker: Lino Demaria (Universita e INFN Torino (IT))

TWEPP_2022_WLT_230922.pdf

11:40 Software Tools for Hybrid Quality Control for the CMS Phase-2 Outer Tracker Upgrade

Fifty thousand hybrid circuits of five different types will be manufactured for the Phase-2 Upgrade of the CMS Outer Tracker. These circuits must undergo a strict quality control process, composed of functional testing and visual inspection, before they can be assembled into modules. The hybrids will be functionally tested first at the manufacturing sites. Afterwards, they will be visually inspected and functionally tested again at CERN or at collaborating institutes. Results from these processes will be stored in the CMS production database. This paper will present the software tools developed to carry out these tasks.

Speaker: Irene Mateos Dominguez (CERN)

Software_Tools_for_Hybrid_Quality_Control-imateos.pdf

Software_Tools_for_Hybrid_Quality_Control-imateos.pptx

11:20 → 12:00 Systems, Planning, Installation, Commissioning and Running Experience

Conveners: Hucheng Chen (Brookhaven National Laboratory (US)), Ken Wyllie (CERN)

11:20 Status and recent extensions of the Caribou DAQ System

Caribou is a flexible open-source DAQ system developed and used within several collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for laboratory and high-rate beam tests and easy integration of new silicon-pixel detector prototypes. It uses common hardware, firmware and software components that are shared across different projects, thereby reducing the development effort and cost for such readout systems significantly. This contribution presents the structure and capabilities of the DAQ system and shows example implementations for recent monolithic CMOS pixel sensors with sub-nanosecond precision requirements for timing measurements.

Speaker: Eric Buschmann (CERN)

caribou_twepp (3).pdf

11:40 Development of a high-rate Scalable Readout System for gaseous detectors

The RD51 collaboration pursues research activities on Micro-Pattern Gaseous Detectors. One of its achievements is the development of a common multi-purpose readout system, the RD51 Scalable Readout System (SRS). Successfully established within the community, the SRS was enhanced by integrating the ATLAS/BNL VMM3a front-end ASIC. The outcome is a self-triggered continuous readout system for any kind of gaseous detector. It allows to record particles with MHz interaction rate, measuring their energy, space and time in small R&D set-ups (0.2k channels) to mid-sized experiments with multiple detectors (2.5k to 5k channels).

Speakers: Jonathan Floethner (University of Bonn (DE)), Lucian Scharenberg (CERN, University of Bonn (DE))

award2022_scharenberg.pdf

twepp2022_lucian-scharenberg.pdf

12:00 → 12:20 Closing

12:00 Closing

Speaker: Alex Kluge (CERN)

20220923TWEPPclosing.pdf

20220923TWEPPclosing.pptx

12:30 → 14:00 Lunch

14:00 → 17:00 Tutorial: Design and layout practises for high-speed design signal integrity - Jean-Michel Capitan