Design and layout practises for high-speed design signal integrity
A 3-hour training tutorial will be held for interested participants on Friday, September 23, 2022 in the afternoon.
The mandatory registration for the tutorial is available during the TWEPP registration process and costs 80 Euro.
The training will be held by Jean-Michel Capitan who already gave an invited talk during TWEPP 2019.
The TWEPP 2022 tutorial will cover
Design and layout practises for high-speed design signal integrity
- different types of PCB materials and their impact on signal integrity;
- definition of signal band width;
- impact on return and insertion loss on power budget;
- roles of pre-emphasis and de-emphasis;
- redrivers vs retimers on high-speed buses;
- PCB HDI structures;
- good layout practises and layout traps for traces and passive components;
- role of stitching vias and stitching capacitors;
- the stubs problem and possible solutions;
- copper roughness impact on signal integrity;
- hybrid PCB structures;
- length matching error impact in differential pairs;
- the impact of glass waves types in PCBs;
- the different crosstalk types and good layout isolation practices;
- good routing of decoupling capacitors;
- demo on the SI-oriented PCB design tool suite: POLAR Si9000e and Speedstack.
