HKROC is an ASIC designed to readout the photomultiplier tubes of the Hyper-Kamiokande experiment. With a large number of channels and stringent readout requirements in terms of noise, speed and dynamic range, the ASIC is very challenging and innovative. Each HKROC channel embeds low-noise preamplifier-shapers, a 10-bit SAR-ADC for the charge measurement (up to 2500 pC) and a TDC for the...
The MIP Timing Detector (MTD) is introduced in the CMS experiment to measure the production time of MIPs. Power Conversion Cards (PCCs) regulate low-voltages in the MTD barrel region. They host three radiation and magnetic field tolerant DC-DC converters. The height of the PCC is limited to 7 mm. This necessitated the development of custom inductors and shields. Additionally, the CMS...
RD53 Collaboration is a joint effort between ATLAS and CMS that was
established in 2013, and extended in 2018, to develop readout chips
for the HL-LHC pixel detectors in 65nm technology.
Main operational constraints for the readout electronics are: the
extremely harsh radiation environment (1 Grad), high hit (3GHz/cm2)
and Trigger rates (4 MHz), high data rate readout (5 Gb/s).
This work...
The upgraded CMS tracker for HL-LHC is going to require more than 200 kW power. Two different powering strategies are being adopted for the Inner Tracker and the Outer Tracker. The talk describes the two powering schemes and discusses the intrinsic constrains. Specifications for the powering units and for the cables of the two systems are outlined in combination to preliminary results with prototypes
The high luminosity upgrade for the LHC at CERN requires a complete overhaul of the current inner detectors of ATLAS and CMS. A serial powering scheme has been chosen to cope with the constraints of the new pixel detectors. A prototype stave consisting of up to 8 quad modules, based on the new readout chips developed by the RD53 collaboration in 65 nm CMOS technology, RD53A and ITkPixV1, has...
The upgraded high-luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon Calorimeter readout operating at 40MHz with 16-bit dynamic range. The COLUTA is a 65nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application, coupling a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC. A Digital Data...
ASICs are important components in many HEP detectors and their functional simulation ensures successful operation while minimizing the number of long production cycles. Three radiation-tolerant ASICs (HCC, AMAC, and ABC) will perform the front-end readout, monitoring, and control of the outer layers of the ITk Strip particle tracker for the HL-LHC ATLAS detector. Simulated verification with...
An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. Furthermore, it provides readout for the DT detector. The ATCA processor is based on a Xilinx XCVU13P FPGA, it receives data via 10 Gbps optical links and transmits track segments via 25 Gbps optical links. The...
This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the final version of the Short-Strip readout ASIC for the CMS Outer-Tracker PS-module. The ASIC performance is characterised at different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises...
The ToASt ASIC is a 64 channel integrated circuit designed for the readout
of the Silicon Strips that will equip the Micro-Vertex Detector of the PANDA
experiment.
The ASIC is synchronous to a 160 MHz clock, which defines also the
time resolution. A common time stamp is distributed to all channels to
provide a common time reference for time of arrival and time over threshold...
The upgrade of the CMS detector for the high-luminosity LHC will include track-finding for the first time in the Level-1 trigger, enabling Particle Flow reconstruction of every event in addition to comprehensive pileup mitigation. The Correlator trigger will reconstruct isolated leptons and photons, hadronic jets, and energy sums, assisted in many cases by machine learning to benefit from the...
ALTIROC2 is the first full-scale 225-channel ASIC prototype designed for LGAD (low Gain Avalanche Diodes) readout, as part of the new ATLAS HGTD detector foreseen for the High Luminosity-LHC upgrade. The scientific goals require to detect charges as small as 2 fC with a 95% efficiency and to exhibit a 25 ps jitter for 10 fC input charge with less than 5 mW/channel. The 2x2 cm² chip was...
The LHC interaction rate at ALICE will be increased to 50 kHz in Pb--Pb collisions and 1 MHz in pp collisions. In order to read out data at these interaction rates the ALICE Central Trigger System was upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System, based on a Passive Optical Network. The main hardware is a universal trigger board based on the Xilinx...
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC1 has been extensively tested, another round of beam test is now on going at Fermilab since March 2022. The performance of ETROC1 will be summarized, with emphasis on the main issue learned on the 40MHz noise after bump bonded with LGAD sensor and most recent...
The design of the Sector Logic (SL) for the ATLAS Level-0 muon trigger at HL-LHC and the milestones achieved on the hardware and firmware developments are presented. The first prototype of the SL board was produced, and all the functions have been demonstrated and confirmed. Fast tracking using Thin Gap Chamber (TGC) hits, a core part of the Level-0 muon trigger, has been developed for full...
The MDT Trigger Processor (MDTTP) processes muon trigger candidates along with Monitored Drift Tubes (MDT) hits to improve the accuracy of the transverse momentum calculation at the first-level (level-0) of the muon trigger. The challenge would be processing all candidates in a bunch crossing to meet latency requirements of High-Luminosity LHC. The MDTTP hardware is based on the Apollo ATCA...
The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD), which will consist of barrel and endcap timing layers, BTL and ETL. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs read-out by TOFHIR2 ASICs in the front-end system. A resolution of 30 ps for MIP signals is expected at the beginning of HL-LHC operation, degrading to 60 ps at...
Measuring charged-particles with 10ps time resolution using innovative 3D trench-type silicon pixel sensors
Future collider experiments operating at very high instantaneous luminosity will greatly benefit in using detectors with excellent time resolution to facilitate event reconstruction. As an example, when the LHCb experiment will operate at 1.5x1034/cm/s after its Upgrade2, 2000 tracks...
The Global Trigger will bring even-filter-like capability to the High-Luminosity trigger system of the ATLAS experiment. Its several firmware-based nodes will run on identical hardware, the Global Common Module, an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was developed to mitigate risks of complex design...
We present the timing measurements performed using the Timespot1 ASIC after hybridization onto a sensor pixel matrix featuring 32x32 channels. The ASIC is fabricated in CMOS 28-nm technology and integrates 1024 readout pixels, each equipped with a fast Analog Front End and a high-resolution TDC. The sensor is a matched matrix of 1024 3D silicon sensors, having pitch of 55 µm and processed in a...
The implementation of a 64-channel ASIC for the readout of Silicon Photomultipliers in space experiments is described. Each channel embeds 256 memory cells which sample the input information at 200 MS/s. A single cell includes a sampling capacitor, a single-slope analog-to-digital converter and a digital control logic. The digitization is carried out only if a trigger signal validates the time...
We present a high speed Phase Locked Loop (PLL) which is designed to provide high speed clock for a pixel chip to transmit the serial data off chip. The pixel chip is designed to read out the charge of a beam monitor which is part of the CSR external-target experiment at HIRFL in China. The PLL consists of a differential ring oscillator, a digital divider, three-state phase frequency detector,...
A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks of 40 MHz, 80 MHz, and 640 MHz in the ALTIROC chip. The phase shifter is a two-step architecture, consisting of a coarse-phase shifting and a fine-phase shifting with a 97.7 ps step. The fine delay is a DLL-based structure operating at 640 MHz. The clocks are programmable independently and share one DLL...
A line driver with configurable pre-emphasis is implemented in a 65nm CMOS process. The driver utilizes a three-tap Feed-Forward Equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the Unit Interval (UI) via an 8-stage Delay-Locked Loop (DLL) and digital interpolator (DI). One can also control the output amplitude and source impedance...
We present the design of a prototype MAPS sensor MIC6 based on a 55 nm Quad-well CMOS Image Sensor process for the high energy physics experiment vertex detector application. A new node-based, data-driven, parallel readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. The size of MIC6 is 2.8 mm × 2.8 mm, which contains a pixel matrix...
The Inner Tracker silicon strip detector (ITk Strips) is a part of the ATLAS upgrade for the HL-LHC. The detector readout and control is accomplished by the interaction of three on-module custom ASICs (ABCStarv1, HCCStarv1 and AMACstar). All ASICs are designed with protections against Single Event Errors. Their resilience at the system-level can be tested using the Board for Evaluation of...
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. Two versions, CIC1 and CIC2, were tested successfully in 2019 and 2021...
The stability of the clock distributed by the first version of the Barrel Calorimeter Processor (BCP V1) to the front-end electronics has been evaluated and compared with the required performance as specified for the phase 2 upgrade of the CMS Barrel Electromagnetic Calorimeter (EB). The evaluation setup emulated a full clock branch of the planned EB system through multiple stages. The...
The new Muon-Central-Trigger-Processor-Interface (MUCTPI) is part of the upgrade of the ATLAS Level-1 trigger system for the upcoming run of the Large Hadron Collider at CERN. High-end FPGAs receive and process muon candidate information arriving on 208 high-speed optical serial links, while the board is controlled by a SoC. Processed trigger information and summary data are sent to other...
We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features:...
The CMS experiment will replace its endcap calorimeters with a High Granularity Endcap Calorimeter (HGCAL) as part of the upgrades for High Luminosity LHC. The HGCAL readout system includes the Endcap Trigger Concentrator (ECON-T) ASIC to help manage the immense data volume associated with the trigger path of this six-million channel “imaging” calorimeter. Each ECON-T ASIC handles 15.36 Gbps...
The University of Liverpool HV-CMOS R&D group develops depleted monolithic active pixel sensors (DMAPS) for use in high radiation environments. In this contribution, we will present an overview of results from the latest chip, UKRI-MPW0. The contribution will focus primarily on the design of three sub-circuits, a bipolar junction transistor (BJT) based bandgap reference (BGR), a fully CMOS...
The tight space constraints of the ATLAS ITk Pixel system motivate the design of large-scale flex circuits for carrying low-voltage power, high-voltage sensor bias, and command/data transmission. These circuits extend over long distances in the barrel or large areas in the endcap rings, and they pose unique design challenges. We report on the design and prototyping of large-scale flex circuits...
Motivated by upcoming large upgrade projects at PSI and due to increasing demands for performance (handling more data, faster processing) in various subsystems of the accelerator and beamlines, our electronics and control system experts had the task to evaluate alternatives to the existing VME technology and build a new portfolio of electronic hardware tools accordingly. CompactPCI-Serial was...
An FPGA-based DAQ has been developed for collecting position information from several position-sensitive RPCs to reconstruct the tracks of cosmic muons in a muon scattering tomography setup. An 8-channel ultra-fast preamplifier discriminator NINO ASIC has been used in the front-end for the acquisition of current signals induced on readout channels of the RPCs. The DAQ has been designed for...
The custom design, radiation and magnetic field tolerant step-down DC/DC converter system was developed to supply LV power for the ATLAS ITk Strip Detector segments. The system is modular and consists of custom frames with embedded cooling plates and insertable boards containing two or four output channels. Each channel comprises a 48-to-11 V DC/DC converter, hardware overcurrent and...
The CPPM group has long been designing and testing HV-CMOS blocks to complete monolithic chips in various technologies (TJ180, LF150, AMS) in the framework of several collaborations. In 2020, we participated in the MLR1 run in TowerJazz 65 nm technology through CERN’s EP-R&D WP1.2, by designing a ring oscillator test chip. Its aim is to characterize the standard cells of this technology and...
Heterogeneous SoC-FPGAs are extremely valuable in custom instrumentation. We present the joint development of the DTS-100G by DESY and KIT. It is built around a Xilinx Zynq Ultrascale Plus and offers all available high-speed transceivers using QSFP28, Firefly28G, FMC, and FMC+ interfaces. The board is not specialized to a single application and can be used as a generic DAQ platform for various...
With the High Luminosity upgrade of the LHC we expect increased instantaneous luminosities up to 5x10^34 cm^-2s^-1, or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of the three new muon sub-detectors. The readout electronics for ME0 must be designed to accommodate high data rates and...
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a 564 ps output rise time, and a projected jitter value on the order...
ATLAS detector Phase-II upgrade for the High Luminosity Large Hadron Collider (HL-LHC) affects all major ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses the most advanced FPGAs and optical modules to provide high input and output bandwidth and substantial processing power. The Global Trigger Versatile Module (GVM) hosts...
Hamlet has developed a modular gamma detector that can be operated in a hostile environment. The system is based on a matrix of CsI crystals readout with thermalized SiPM, and a digitizer board designed for the Mu2e electromagnetic calorimeter and customized for this project. Front-end electronics is based on the MUSIC chip, a custom VLSI component developed by the University of Barcelona. The...
This study shows a pattern recognition system based on Hough transform implemented on last generations of FPGA families, as the Xilinx UltraScale+. This investigation started from the ATLAS HTT project, and now it is proposed in general for the LHC Phase-II trigger upgrades HEP experiments, especially to those which aim at fast tracking capabilities. We have designed a Hough transform software...
The electronics of the ATLAS Tile Calorimeter will be replaced for the HL-LHC. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated during seven test beam campaigns, and inserted into the ATLAS experiment in 2019. The Demonstrator module was build with backward...
In order to meet power and heat budget in large multichannel detector systems, an early data reduction by the means of signal feature extraction is necessary.
We are contributing to this topic, studying different approaches from analog and digital signal processing, investigating the influence of parameters like bandwidth and digitizer resolution. In a second step, we are looking into the...
PLUME (Probe for LUminosity MEasurement) is a dedicated luminosity meter (luminometer) for the LHCb detector which will operate during Run 3 at a luminosity level five times higher than in the previous runs. It was designed to measure, in real time, the instantaneous luminosity with an accuracy better than 5 %.
The detector relies on the registration of Cherenkov light emitted...
LHCb is undergoing a major upgrade to cope with LHC RUN3's increased luminosities and a trigger-less 40 MHz read-out to improve on many world-best physics measurements. A light and homogeneous tracker based on plastic scintillating fibers (SciFi) driven by 524k SiPM channels is being installed downstream of the LHCb dipole magnet. A Test System is in use to ensure the Quality Control of each...
Developing and implementing algorithms for detector read-out using FPGAs is traditionally done by using a hardware description language like VHDL, Verilog, or System Verilog. In the proposed approach here, we discuss an alternative way using higher level languages like the Intel HLS Compiler. Intel HLS supports C++17 standard and is ideal to apply methods from Modern C++ to implement complex...
The ATLAS ZDC detectors located in the LHC tunnel detect far-forward neutrons from interactions during lead-lead collisions. PMT signals are transferred over fast air-core cable at distance of 200 m to electronics room. A new ZDC-LUCROD readout module is a 9U VME board capable of processing signals from 8 channels with an FADC sampling rate of 320 MHz. The primary modification wrt....
Beyond Run$4$ of the LHC the instantaneous luminosity in the LHCb detector is going to be raised to $1.5\mathrm{x}10^{34}\mathrm{cm}^{-2}\mathrm{s}^{-1}$. To achieve stable operations and precise tracking, it is planned to upgrade the complete LHCb tracking system.
The downstream trackers have to be upgraded to withstand the increased radiation and occupancy at a similar or lower material...
Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The CMS pre-production chip...
We report on our latest developments of a planar fiber-chip-coupling scheme, using angle polished, polarization maintaining (PM) fibers. Most integrated photonic chip components are polarization sensitive and a suitable way to launch several wavelength channels to the chip with the same polarization is the use of PM fibers. Those impose several challenges at processing and handling to achieve...
The high-luminosity upgrade to the LHC (HL-LHC) requires an all new, silicon-based inner detector (ITk strips). The AMACStar is one of three radiation hard ASICs that will be installed on the ITk strip modules. Its function is to autonomously monitor and control the temperatures, voltages, and currents in the detector modules, an essential feature for the ITk detector modules. A comprehensive...
TSPC dynamic logic is widely used in high-speed circuits like high-speed SERDES or frequency dividers. TSPC flip-flops are characterized by their high operation speed and low power consumption when compared with static flip-flops. Due to the relatively high leakage currents in the modern CMOS process, the use of leakage protection techniques of the storage nodes of TSPC logic is mandatory. In...
The CERN RD50 CMOS working group develops the RD50-MPW series of monolithic CMOS sensors for potential use in future high luminosity experiments such as HL-LHC and FCC-hh.
In this contribution, we will present an overview of the RD50 High Voltage-CMOS activities, focusing on the design of RD50-MPW3, the latest chip of this series, and the readout electronics beyond the chip. We will give a...
The CMS Phase II High-Granularity Calorimeter (HGCAL) relies on passive boards known as wagons to transmit signals from silicon sensor modules to upstream electronics for further processing. Such wagon boards face many design constraints that result in over 50 unique varieties, each of which requires the precise placement of dozens of components onto a PCB layout. A suite of tools has been...
Precision timing at 10ps levels will be transformative at future collider experiments. In case of high-energy, high-luminosity hadron colliders, including Run5/6 upgrades of HL-LHC, an integrated four-dimensional tracker with timing resolution of 10-30ps can drastically reduce the combinatorial challenge of track reconstruction at very high pileup densities. 4D trackers and timing layers are...
For the High-Luminosity Large Hadron Collider, the trigger and data acquisition system of the CMS experiment will be entirely replaced. Novel design choices have been explored, including ATCA prototyping platforms with SoC controllers and newly available interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger analyses will be performed through sophisticated...
*As part of the CMS Phase Two Outer Tracker upgrade, a test card was developed to test the sensor bias high voltage filters present in the PS-FEH-R hybrids. The test card can test up to four hybrids at the same time. The test functions are voltage measurement, leakage current measurement and resistance measurement. A software test procedure was written to control the card and to perform the...
This contributions presents the implementation of the CBM-TRD cluster finder. The cluster finder is implented with Vitis HLS in an FPGA.
The CBM experiment at FAIR will focus on rare probes of the QCD phase diagram at high net-baryon densities.
The free streaming DAQ has to process up-to 2 TB/s of raw data. This data undergo online event selection, where 4D track reconstruction is necessary....
COLDATA is the data concentrator ASIC for the Liquid Argon Time Projection Chamber (LArTPC) Far Detector of the Deep Underground Neutrino Experiment (DUNE). This ASIC will operate for its lifetime at cryogenic temperatures immersed in LAr. Two COLDATA, eight ColdADC, and eight LArASIC front-end ASICs are placed on each Front-End Motherboard (FEMB) in the LArTPC. Each COLDATA concentrates...
A high resolution W-Si preshower detector is proposed for the FASER experiment at CERN to enable the measurement of new physics signals related to Long Lived Particles. For this purpose, a 1.5x2.2 cm2 monolithic silicon active-pixel detector is being developed. The detector will integrate ultra-fast, low-noise front-end electronics in 65 μm side hexagonal pixels. The system is designed to read...
The CMS experiment 40MHz Scouting project is aimed at intercepting the data produced at the level of the detectors' front-end without the filters induced by hardware-based Triggers. A first 40MHz Scouting implementation is realized by reading a slice of the Drift Tube (DT) muon detector, equipped with so-called Phase-2 Upgrade front-end boards. The data are transferred via high-speed optical...
The data link from the detectors to the back-end stage must keep up with the requirements from the upcoming generation of High Energy Physics experiments. Pushing the limit of the Non-Return-to-Zero (NRZ) modulated signals, a line rate of up to 28 Gbps can be realized. In this talk, the implementation of the DART28 demonstrator system based on FPGA platforms from Xilinx and Intel will be...
The MOnolithic Stitched Sensor chip (MOSS) is a development prototype towards the innovative ITS3 vertexing detector for the ALICE experiment at the LHC. Designed using a 65 nm CMOS Imaging technology, it aims at profiting from the stitching technique to construct a single-die monolithic pixel detector of 1.4 cm x 26 cm. The MOSS chip is one of the prototypes developed within CERN-EP R&D to...
A series of monolithic active pixel sensor prototypes were manufactured in the TPSCo 65 nm ISC imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4x4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel sizes (10um - 25um),...
Neural Network (NN)-based inference deployed in FPGAs or ASICs is a powerful tool for real-time data processing and reduction. FPGAs or ASICs may be needed to meet difficult latency or power efficiency requirements in data acquisition or control systems. The software package, hls4ml, was designed to make deploying optimized NNs on FPGAs and ASICs accessible for domain applications. We will...
The FELIX system is used to interface the front-end electronics and the commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. In the current version of FELIX, RDMA communication is implemented using software on both ends of the links. Improvements of the data...
The MONOLITH ERC Advanced project aims at producing a monolithic silicon pixel ASIC with picosecond-level time stamping by using fast SiGe BiCMOS electronics and a novel sensor concept, the Picosecond Avalanche Detector (PicoAD). A first ASIC prototype, featuring fast electronics and hexagonal pixel with 100µm pitch, confirms that the PicoAD principle works and achieves time resolutions better...
MiniCACTUS is a monolithic CMOS sensor designed for tagging Minimum Ionizing Particles at the 100 ps level. The sensor features an array of diodes, without internal amplification, of surface 1.0 mm² and 0.5 mm², with an analog front-end and discriminator per pixel. A time resolution of 88 ps has been measured on a 0.5 mm² pixel from a 200 µm-thick sensor tested at CERN. 300 micron and 200...
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the functions of four Endcap Layer Readout Chips (ETROCs), each including a PLL, a fast command decoder, the pixel and global data readout, and an I2C target. Based on the actual ETROC design, the firmware is implemented and...
The design and measurement results of a SoC readout ASIC, called FLAME, developed for the electromagnetic calorimeter at the future linear collider are presented. The FLAME consists of 32 channels with variable gain front-end, fully differential shaper, and a 10-bit SAR ADC, working at 20 MSps, in each channel. All ADC samples are streamed out by two 5.2 Gbps serializers. Two testbeam...
The increase in the complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes are strong advocators for employing a System-on-Chip (SoC) design integration methodology. This contribution will present a survey of open-source RISC-V based SoC design platforms and the results of an evaluation study in terms of performance, power...
At the HL-LHC, the number of proton-proton collisions in one bunch-crossing (called pileup) increases significantly, putting more stringent requirements on the LHC detectors electronics and real-time data-processing capabilities. The ATLAS LAr calorimeter measures with an excellent resolution the energy of particles produced in LHC collisions. The energy is computed in real-time using optimal...
The discovery of a large fab-to-fab variability in the TID response of the CMOS technologies used in the design of ASICs for the particle detectors of the HL-LHC triggered a monitoring effort to verify the consistency of the CMOS production process over time. As of 2014, 22 chips from 3 different fabs in 130nm CMOS technology and 10 chips from 2 different fabs in 65nm CMOS technology have been...
SAFIR (Small Animal Fast Insert for MRI) is a PET (Positron Emission Tomography) insert for the Bruker BioSpec 70/30 pre-clinical MRI (Magnet Resonance Imaging) system. It is aiming at truly simultaneous PET/MRI acquisitions allowing imaging time frames of seconds instead of minutes. SAFIR is intended for operation at up to 500MBq injected activities in mice, 10x higher than in other systems....
AGIPD is one of the detectors developed for the experimental stations of the European XFEL, one of the newest free-electron laser sources. The detector pixels write high dynamic images from single up to 104 12.5 keV-photons at a maximum frequency of 4.5 MHz operating in a burst mode – read-out is performed between the bursts. There are certain challenging optimizations done to the...
For the high luminosity upgrade to the LHC, the ATLAS inner detector will be replaced by an all-silicon tracker (ITk) consisting of two systems: pixels and strips. The HCCStar and AMACStar are ITk strips ASICs vital for performing the system readout, and monitoring and control.To ensure these ASICs will successfully operate in the high-radiation environment of the HL-LHC, these ASICs need to...
HDM is a new Hybrid Detector for medical application combining a tissue equivalent microdosimeter and a LGAD-based (Low Gain Avalanche Diode) particle tracker with the goal of improving the radiation quality description. Energy deposition information after analog processing is recorded with 3 ADC mounted on a FPGA based solution, while tracking information is processed by a dedicated readout...
The CERN EP R&D WP 1.2 aims to develop state-of-art monolithic pixel detectors using accessible modern CMOS processes. The TPSCo 65nm process is a suitable candidate and its radiation tolerance and sensor performance are therefore being studied. The impact of the back bias on the transistor behavior has also been measured to provide the designers with accurate models. This process shows...
The High Energy Particle Detector (HEPD-02), part of the CSES-02 satellite, is a compact particle
detector composed by a 3-layer pixel silicon tracker and a calorimetric system.
HEPD-02 will be the first spaceborne instrument using Monolithic Active Pixels (MAPS) in place of micro-strips detectors;
the tracker is composed of 150 CMOS 180 nm sensors, based on the development carried out for...
The readout system of the Mu2e electromagnetic calorimeter is composed of a front-end which collects and transmits the SiPM signals to a waveform digitizer performing a 200 MHz sampling. The Mu2e harsh operational environment (Total Ionizing Dose (TID) of 12 krad and neutron fluence of 5x1010 n/cm2 @ 1 MeVeq (Si)/y, 1T magnetic field, level of vacuum of 10-4 Torr) has made the design...
A cost-effective single-die pixel-detector hybridisation technology based on Anisotropic Conductive Films (ACF) is under development, to replace fine-pitch bump bonding with thermo-compression of conductive micro-particles embedded in an epoxy film. It can also be used for the integration of hybrid or monolithic detectors in modules, replacing wire bonding or solder-bumping techniques. An...
A bandgap voltage reference, an 8-bit binary-weighted Digital to Analog Converter (DAC), a rail-to-rail operation amplifier and a scalable low voltage signaling (SLVS) transmitter and receiverhave been developed as macro blocks in 28 nm CMOS technology for the future upgrades for the high luminosity LHC. This work summarizes the design approach at the schematic and layout level. Practical...
The High Granularity Timing Detector for the ATLAS upgrade is under construction to meet the challenges of the HL-LHC. In order to connect a module, the basic detector element, to the surrounding peripheral electronic board, a flexible printed circuit (FPC) is proposed as an interconnection for data transmission and power distribution. Identical design for the FPC is required except their...
Multi-chip modules using the MALTA1 pixel sensor have been built to validate the direct transfer of data from chip to chip and to read out the module via one chip only. Novel interconnection technologies such (ACF, nanowires) have been investigated to build a compact module. A lightweight flex with 17um trace/spacing has been designed that will allow compact packaging with a direct attachment...
The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown. A new silicon Inner Tracker (ITk) will contain five innermost pixel layers equipped with new sensors and readout electronics capable to improve the tracking performance, cope with the high particle multiplicity and work in a high luminosity environment. In order to standardize modules of the...
The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two "snapshots" of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each...
The TPSCo 65 nm ISC technology is under study in the framework of the CERN-EP on monolithic active pixel sensors (MAPS) for High Energy Physics (HEP) applications, and the ALICE ITS3 upgrade project, for which a wafer-scale stitched MAPS sensor is under development. This contribution presents designs and measurement results for Bandgap Reference (BGR) and Temperature Sensor (TS) prototypes...
The ATLAS experiment is currently preparing for an upgrade of the inner tracking detector for High-Luminosity LHC. The new tracker, ITk, employs an all-silicon detector with outer Strip layers. The building block of the ITk Strip barrel is the stave which consists of a low-mass support structure hosting the common electrical, optical and cooling services as well as 28 silicon modules. In this...
A method of automating the visual inspection of ATLAS upgrade strip modules is shown. The visual inspection of the hybrids is a time consuming part of the quality control during module production. A method of detecting and classifying the SMD components on the hybrids using an object detection neural network was investigated. The results show that the amount of hybrids that needed to be check...
The CMS detector will undergo an upgrade for Phase-2 of the LHC
program. The back-end electronics will be implemented as ATCA node
boards, connecting to the central systems via a custom `DTH' hub
board.
Instead of a traditional distribution tree, the CMS Phase-2 Trigger
and Timing Distribution System (TCDS) will use a configurable
switching network to connect multiple hardware `run...
We report a pluggable radiation-tolerant PAM4 optical transmitter module called GBT20 (Gigabit transmitter at 20 Gbps) for the high-energy physics experiments. The core of GBT20 is an ASIC GBS20. GBT20 uses an OSFP or firefly connector to input 16-bit data each at 1.28 Gbps. GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. A...
Establishing a reliable and efficient method to control electronics system consisting of many boards is critical in the system design. Among unique requirements for the control in high energy physics experiments, we propose a maximally-automated and self-driven scheme for a system that exploits FPGAs, SPI flash memory devices, and high-speed fixed-latency optical links. We have implemented our...
A slim vertical slice of the CMS Outer Tracker has been assembled at the Tracker Integration Facility at CERN. It includes the final 2S and PS front-end hybrids with an optical link to the back-end ATCA system, comprising the Data, Trigger and Control (DTC), DAQ & Timing Hub (DTH) and Track Finder (TF). The performance of the system will be described, such as the real-world cooling limits of...
The LHC phase-2 upgrades will pose unprecedent challenges in terms of timing stability to the clock delivered to thousands of nodes in an experiment. Slow phase variations could dominate the overall timing stability in a clock recovered from a high-speed optical link.
The TCLink is an integrated protocol agnostic FPGA core that can monitor and correct slow phase variations in high-speed...
We present the design and performance of the Hexaboard, a complex hexagonal multi-layer PCB equipped with multiple HGCROC ASICs to read out the signals from silicon pads with low noise and large dynamic range. The Hexaboards are glued to silicon sensors and connect to them via wire bonds through holes in the PCBs. The Hexaboard also connects to mezzanine boards for powering, data concentration...
Proof of concept of a 2-channel Data Acquisition system for Astroparticles detectors.
The astroparticle detector is a 1000Lts Water Cherenkov Detector plus 2 scintillating pads.
This detector allow to perform measurements of the Vertical Equivalent Muon that are used to improve the calibration factors.
This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed....
This paper presents a dual frequency PLL designed to support data transmission in next generation particle physics detectors. The PLL is designed in a 65nm CMOS process and operates in two frequency modes 1.25GHz in the lower frequency mode and 7GHz in the higher frequency mode. A PRBS generator is integrated with the PLL to enable testing and the design occupies 0.110um2 of silicon space. The...
This work presents a versatile system that is dedicated for the testing of various integrated circuits in radiation (e.g., FPGAs, ASICs). This system allows to power the device under test (DUT), and to monitor and read out in real time various parameters: power consumption (100 µV and 100 µA resolution), and various operational parameters. The system has built-in features to detect and test...
The High-density High-precision High-speed Front-End Electronic (HFEE) is widely used in the high hit rate gas detectors. The design and characterization of a HFEE prototype is presented in this paper. The prototype chip is composed of four channels and each channel consists of a charge-sensitive preamplifier, a pole-zero cancellation circuit, a S-K filter and a gain amplifier. The simulations...
This work presents the design and characterization of a radiation hard bandgap reference circuit fabricated in a 110nm CMOS technology for the Main Demonstrator chip of the ARCADIA project. The design, based on a current-mode approach in order to be able to output a smaller than 1.2V reference voltage, employs diode-connected MOSFETs instead of BJTs to enhance the radiation hardness and a...
The ITS 3 project within the ALICE Experiment is developing an innovative vertex tracker to be installed during the Long Shutdown 3 of the LHC. Based on a commercial 65 nm CMOS imaging technology, it consists of cylindrical sensors that can be installed as close as 18 mm to the interaction point.
In order to validate the technology, test chips were produced in a first submission named MLR1....
The CROC-V1 readout front-end (FE) chip was designed by the RD53 collaboration for the CMS Phase-2 Inner Tracker Upgrade. It is designed to cope with the extreme radiation and hit rates of the HL-LHC and it is based on the 65 nm CMOS technology and a novel analog FE design featuring linear charge to Time-over-Threshold (ToT) conversion. In this contribution, the characterization measurements...
To cope with an increase of luminosity at Run-3 of the LHC, a new trigger readout path has been installed to the Liquid Argon Calorimeters.
More than 1500 boards of the legacy system were refurbished and re-installed, 124 new on-detector boards equipped with large FPGAs were added to digitize the calorimeter trigger signals, and all the monitoring and control infrastructure is being adapted...
A high-speed, low-power analog front end (AFE) utilizing a current-mode signal path has been designed for 4D tracking applications where precision time resolution of order 50 ps is a requirement. The preamplifier concept is based on a prior art current-feedback CMOS topology [1]. The power consumption of the AFE is 6 uA at 0.9 V process voltage. An on-chip test bench comprised of a variable...
Three new Point-of-Load (POL) converters, suitable for the High Luminosity – Large Hadron Collider (HL-LHC) experiments and for space/avionic applications, are under development. The two DCDC converters, called bPOL48V and rPOL48V, allow a significant improvement in the power delivery requirements as they can provide higher power at an increased input voltage of 48V, compared to existing...
To cope with the challenges posed by the High-Luminosity LHC, the CMS experiment will feature a new silicon tracker. The modules for the inner tracker are hybrid silicon pixel modules based on a new readout ASIC, developed by the RD53 Collaboration, capable of sustaining higher hit rates and radiation levels and enabling the use of serial-powering chains. The qualification of the latest...
The CMS tracker phase-2 upgrade modules are required to reach noise levels close to the ones expected from the analog front-end attached to an ideal pixel/strip. Module prototypes, featuring the latest and final prototype hybrids before the production, showed noise that was higher than the expected which could pose a problem in terms of achieving the hit efficiency target. Investigations that...
Latency and computational resources are key constraints for high bandwidth, low latency trigger systems. In these systems, even if a GPU/FPGA is used to accelerate computation, transferring data between components is still a costly operation for the host. In this work, we study a computational storage system employing FPGAs to detect supernova neutrino bursts, with a particular focus on LArTPC...
ASICs designed for HEP embed always more digital components and require complex and critical verifications. Prototyping enables implementations of digital part of ASIC in programmable components such as FPGA. Interactions with external devices such as DAQ, micro-controller or other FPGA are then possible. Debugging of internal firmware or complex stimuli becomes easier and faster than...
The Front-End Link eXchange (FELIX) system is a new ATLAS DAQ component designed to meet the evolving needs of detector readout into the High-Luminosity LHC era. FELIX acts as the interface between the data acquisition; detector and trigger timing and systems; and new or updated trigger and detector front-end electronics. FELIX routes data between custom serial links from front-end electronics...
The planned MALTA3 DMAPS designed in the standard TowerJazz 180 nm Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x1015 MeV neq/cm2. The effectiveness of these changes have been demonstrated in recent measurements with a small-scale mini-MALTA demonstrator chip. Proposed...
Recurrent dielectric breakdowns on the cryogenics instrumentation during the CERN LHC Electrical Quality Assurance (ELQA) campaigns led to an investigation of their root causes. During the CERN Long Shutdown 2 (LS2), several weaknesses were identified like floating wires or cable screens, cabling non-conformities, connector assembly issues, and weakness of the electronic conditioning cards....
For the CMS tracker Phase-2 upgrade new modules with silicon strip sensors are being developed. Each module features a Service Hybrid (SEH) responsible for communication with the tracker back-end and power distribution to the module components. Here, a two stage DC-DC conversion scheme is used for the supply of low voltage. For modules using the latest generation of SEHs an increase in module...
Single photon sensitive detectors used in high energy physics are required to cover very large areas, with a strong demand for an ever finer imaging capability. We are evaluating the LAPPD as a possible candidate for future Cherenkov ring imaging detectors, performing tests on a generation I device, which is capacitively coupled to a custom designed anode back plane, consisting of various...
To increase granularity, resolution, and provide longitudinal shower shape information from the ATLAS LAr calorimeters to its level-1 trigger processor, a new radiation-hard board has been designed during the phase-1 upgrade. This Lar Trigger Digitizer Board adapts and digitizes up to 320 detector inputs using custom ADCs and sends the serialized data through 200Gbps optical links. The run...
The operation of CMS at the HL-LHC requires an upgrade of the readout electronics. These new modern micro-electronics require power at precise voltages between 1.2V and 2.5V. We will deliver this power using a 3-stage system, comprising AC-DC conversion to 400VDC followed by radiation-tolerant 12V DC-DC power converters feeding radiation-hard point-of-load DC-DC converter. We have studied an...
Abstract:
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs of voltages or temperatures to an lpGBT ADC channel through a 6-bit decoder. A total of 92x3 dies were fabricated in two batches by the TSMC 130 nm CMOS technology. All of them passed the quality...
The high-luminosity LHC requires a complete overhaul of the ATLAS inner tracker subsystem, including a new silicon-strip charged-particle tracking detector. The HCCStar (Hybrid Controller Chip) is one of three new ASICs for this subsystem. As the interface to multiple binary readout ASICs for the strip detector, the HCCStar buffers and forwards controls signals and trigger and readout requests...
PASTTREC is an 8-channel readout ASIC for the Straw Tube Tracker (STT) and the Forward Tracker (FT) detectors in the PANDA and for the Straw Tracking System (STS) in the HADES experiments, both at the FAIR facility. Since more than 1500 ASICs were produced for both experiments, efficient qualification tests are required. For this purpose, the multi-chip test setup and dedicated verification...
The new electronics of the ATLAS TileCal for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and and mitigates and radiation damage by means of a double-redundant scheme,...
The ITk Strip is a silicon-strip charged-particle detector that is going to be installed in the ATLAS experiment for the HL-LHC. GaNFETs are radiation-tolerant transistors that permit switching off high voltage to malfunctioning sensors. To ensure the reliability of the GaNFETs in the high radiation environment expected for the ITk Strip, a sample of the transistors were exposed to gamma and...
In order to achieve tens-of-ps particles time-tagging performance required at HL-LHC, the CMS clock tree is being upgraded. A radiation-hard fan-out ASIC, named RAFAEL, was developed to distribute the clock and the data to the frontend ASICs of the CMS detectors that require precision timing, including BTL and HGCAL. Its main constraint is a low additive jitter, less than 4 ps RMS, even after...
For readout electronics capable of exploiting the characteristics of 4H−SiC, we are in testing and optimization phase of a single channel circuit to continuously detect single particles up to GHz rates, including statistical pile-up detection by ToT measurements of shaped pulse signals.
Furthermore, we are evaluating an IC with 128 input channels, originally intended for X-ray imaging, which...
RISC-V is an open standard instruction set architecture with a large community that gives access to many resources (such as architecture, operating systems, tool chains, ...). The use of such a processor could be interesting in several ways for the HEP community. For example, it could be used to have a versatile supervisor of complex chips. The purpose of this presentation is to evaluate the...
The Monitoring of Pixel System (MOPSv2) chip is an Application Specific Integrated Circuit (ASIC) foreseen to provide the temperature and the voltage monitoring data of individual front-end detector modules to the Detector Control System (DCS) of the ATLAS ITk Detector.The chip is required to be radiation hard up to an ionizing dose of 500 Mrad, immune to Single Event Upsets (SEUs) and work...
The ATLAS level-0 barrel muon trigger for High-Luminosity LHC will use data from RPC and MDT muon detectors and from the Tile Calorimeter. RPC hit data will be collected by on-detector Data Transmitter and Collector (DCT) boards and will be sent off-detector to the Sector Logic (SL) boards. Within a latency of 390 ns the SL boards should provide muon pre-candidates to the MDT trigger processor...
Currently microprocessors are precluded from the use in several high-energy physics applications due to the harsh radiation present. The STRV-R1 (SEU-tolerant-RISC-V) RSIC-V microprocessor aims to overcome this limitation and replace the custom digital control logic found in current ASICs. A triple modular redundancy (TMR) based protection scheme is applied to protect the RISC-V microprocessor...
During the ATLAS phase II upgrade, the tracking system of the ATLAS exper-
iment will be replaced by an all-silicon detector called the ITk (Inner Tracker)
with a pixel detector as the most inner part.
The control and monitoring data of the new system will be aggregated from an
on-detector ASIC called MOPS (Monitoring Of Pixel System) and sent to the
DCS using a new interface called...
In order to validate the design of the new all-silicon Inner Tracker (ITk) for ATLAS for the HL-LHC, a series of system tests has been performed, to assess the performance of prototype planar and 3D pixel modules arranged into serial power chains mounted on to realistic mechanical structures. In this report, the prototype loaded local supports and test infrastructure is described and the key...
A new silicon-strip charged-particle detector (ITk Strip) is a major subdetector of the future upgrade of the ATLAS experiment for the HL-LHC. The HCC and AMAC chip are radiation-tolerant ASICs that contribute to the front-end readout, monitoring and control of the ITk Strip subdetector. Comprehensive probe station testing procedures have been developed to guarantee the reliability of each...
The LHCb Experiment was upgraded to a trigger-less system reading out the full detector at 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) is a hybrid pixel detector read out by the "VeloPix" ASIC with on-chip zero-suppression. This talk describes a novel way of calibrating the VELO detector based on a dedicated firmware, implemented...
The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. In this work we present the...
The Zero Degree Calorimeters were designed to provide the measurement of the event geometry and the luminosity in heavy ion operation. The readout system was redesigned in order to operate in continuous mode without dead time at 5 MHz event rate. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of about 1 GSps, assembled on an FPGA Mezzanine Card. The...
After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs...
As high readout channel density and compact design become the norm for HEP detectors so is operation at temperatures below the experimental site dewpoint. This increases the importance of humidity and temperature monitoring systems that are also adapted to the detector environment. In what follows we describe the systems we developed targeting compactness, cost and integration to our DCS/DSS...
Silicon Photonics is a promising technology for future HEP experiments and upgrades. Such experiments and upgrades will require high levels of radiation tolerance and Silicon Photonics Modulators have already been shown to be very radiation tolerant when exposed to high levels of TID under certain conditions. We demonstrate for the first time that changing the temperature of Ring Modulators...
Synchronizing the different parts of a Particle Physics detector is an essential part of its operation. In the DUNE liquid argon neutrino detector timing information is transmitted to the readout systems and time-stamped data is sent to the DAQ.
We describe the DUNE timing system, which uses Duty Cycle Shift Keying with 8b10b encoding and a simple message protocol. The system is designed to...
The high radiation dose and the cold environment at the HL-LHC pixel detector regions presents serious challenges for the survival of optical components. Radiation hard twinax cables are developed for the ATLAS ITk pixel data transmission within the pixel detector volume for up to 6m before transitioning to optical links at larger radius where radiation dose is reduced to acceptable level for...
The electronic system of the CMS Drift Tubes (DT) chambers will be replaced to operate during High Luminosity (HL-LHC). The upgraded architecture ships all signals to the backend, where complex logic will be performed with a precision matching the maximum chamber resolution. A demonstrator has been installed during Long Shutdown 2 (LS2) in one of the sixty sectors of the detector. Over LS2 we...
We present the commissioning and the running experience of the CMS GE1/1 system which has been installed in CMS in October 2020. Since then, GE1/1 has been commissioned and it is now ready for LHC Run-3. The GE1/1 detectors are read-out by the VFAT3 chip which communicates with the microTCA backend through the versatile link. Each detector has 24 VFAT3s, 3 GBTx, 3 VTRx, 2 VTTx, and a Virtex-6...
The building blocks of the ATLAS Strip Tracker for HL-LHC are modules that host silicon sensors and front-end electronics. The modules are mounted on carbon-fibre substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card on each substructure side connects up to 28 differential data lines at 640 Mbit/s to lpGBT and VL+ ASICs that provide data serialisation and 10 GBit/s...
The upgrade of the ATLAS ITk strips detector for HL-LHC will employ a custom PCB (Powerboard) for on-module DC-DC conversion, HV switching, and monitoring. This contribution will present the production procedure and mass test system for 15,000 Powerboards. We will also present the challenges identified during prototyping and pre-production and the performance of the Powerboard with the latest...
The CMS BRIL project upgrades its instrumentation for the Phase-2 detector to provide high-precision bunch-by-bunch luminosity and beam-induced background measurements. A part of the CMS Inner Tracker - the Tracker Endcap Pixel Detector (TEPX) - will allocate a fraction of the read-out bandwidth for luminometry. In order to be used for luminosity measurement, TEPX will require a dedicated...
Abstract
This presentation will review the main recommendations of the 2021 ECFA detector R&D roadmap. It will highlight their potential impact on long-term R&D for electronics and outline the envisaged implementation scenario.
Biography
Francois Vasey holds an electronics engineering degree from ETH-Zurich and a PhD degree in optoelectronics from EPF-Lausanne. He joined CERN in 1994 to...
Caribou is a flexible open-source DAQ system developed and used within several collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for laboratory and high-rate beam tests and easy integration of new silicon-pixel detector prototypes. It uses common hardware, firmware and software components that are shared across different projects, thereby reducing the development effort and cost for...
As part of the CMS Tracker upgrade for High-Luminosity LHC, the Inner Tracker community is developing an automated test system for the qualification of the front-end chip (CROC) before the wafer is sent to the company for dicing and hybridization. The procedure takes approximately one day for each wafer to be tested, thus allowing to fully verify the functionalities of all the chips in the...
The RD51 collaboration pursues research activities on Micro-Pattern Gaseous Detectors. One of its achievements is the development of a common multi-purpose readout system, the RD51 Scalable Readout System (SRS). Successfully established within the community, the SRS was enhanced by integrating the ATLAS/BNL VMM3a front-end ASIC. The outcome is a self-triggered continuous readout system for any...
Fifty thousand hybrid circuits of five different types will be manufactured for the Phase-2 Upgrade of the CMS Outer Tracker. These circuits must undergo a strict quality control process, composed of functional testing and visual inspection, before they can be assembled into modules. The hybrids will be functionally tested first at the manufacturing sites. Afterwards, they will be visually...
