Conveners
Trigger
- Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
- Alex Kluge (CERN)
Trigger
- Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
- Alex Kluge (CERN)
Trigger
- Alex Kluge (CERN)
- Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
We present the architecture and current state of prototype firmware of the CMS Level-1 Global Trigger, the final stage of the Level-1 trigger for Phase-2 of the operation of the LHC. Based on high-precision inputs from the muon-, calorimeter-, track- and particle flow triggers, the Global Trigger evaluates O(1000) cut-based and neural-net based algorithms in a system of up to thirteen Xilinx...
An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. Furthermore, it provides readout for the DT detector. The ATCA processor is based on a Xilinx XCVU13P FPGA, it receives data via 10 Gbps optical links and transmits track segments via 25 Gbps optical links. The...
The upgrade of the CMS detector for the high-luminosity LHC will include track-finding for the first time in the Level-1 trigger, enabling Particle Flow reconstruction of every event in addition to comprehensive pileup mitigation. The Correlator trigger will reconstruct isolated leptons and photons, hadronic jets, and energy sums, assisted in many cases by machine learning to benefit from the...
The LHC interaction rate at ALICE will be increased to 50 kHz in Pb--Pb collisions and 1 MHz in pp collisions. In order to read out data at these interaction rates the ALICE Central Trigger System was upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing System, based on a Passive Optical Network. The main hardware is a universal trigger board based on the Xilinx...
The design of the Sector Logic (SL) for the ATLAS Level-0 muon trigger at HL-LHC and the milestones achieved on the hardware and firmware developments are presented. The first prototype of the SL board was produced, and all the functions have been demonstrated and confirmed. Fast tracking using Thin Gap Chamber (TGC) hits, a core part of the Level-0 muon trigger, has been developed for full...
The MDT Trigger Processor (MDTTP) processes muon trigger candidates along with Monitored Drift Tubes (MDT) hits to improve the accuracy of the transverse momentum calculation at the first-level (level-0) of the muon trigger. The challenge would be processing all candidates in a bunch crossing to meet latency requirements of High-Luminosity LHC. The MDTTP hardware is based on the Apollo ATCA...
The Global Trigger will bring even-filter-like capability to the High-Luminosity trigger system of the ATLAS experiment. Its several firmware-based nodes will run on identical hardware, the Global Common Module, an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was developed to mitigate risks of complex design...
