Proof of concept of a 2-channel Data Acquisition system for Astroparticles detectors.
The astroparticle detector is a 1000Lts Water Cherenkov Detector plus 2 scintillating pads.
This detector allow to perform measurements of the Vertical Equivalent Muon that are used to improve the calibration factors.
This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed....
This paper presents a dual frequency PLL designed to support data transmission in next generation particle physics detectors. The PLL is designed in a 65nm CMOS process and operates in two frequency modes 1.25GHz in the lower frequency mode and 7GHz in the higher frequency mode. A PRBS generator is integrated with the PLL to enable testing and the design occupies 0.110um2 of silicon space. The...
This work presents a versatile system that is dedicated for the testing of various integrated circuits in radiation (e.g., FPGAs, ASICs). This system allows to power the device under test (DUT), and to monitor and read out in real time various parameters: power consumption (100 µV and 100 µA resolution), and various operational parameters. The system has built-in features to detect and test...
The High-density High-precision High-speed Front-End Electronic (HFEE) is widely used in the high hit rate gas detectors. The design and characterization of a HFEE prototype is presented in this paper. The prototype chip is composed of four channels and each channel consists of a charge-sensitive preamplifier, a pole-zero cancellation circuit, a S-K filter and a gain amplifier. The simulations...
This work presents the design and characterization of a radiation hard bandgap reference circuit fabricated in a 110nm CMOS technology for the Main Demonstrator chip of the ARCADIA project. The design, based on a current-mode approach in order to be able to output a smaller than 1.2V reference voltage, employs diode-connected MOSFETs instead of BJTs to enhance the radiation hardness and a...
The ITS 3 project within the ALICE Experiment is developing an innovative vertex tracker to be installed during the Long Shutdown 3 of the LHC. Based on a commercial 65 nm CMOS imaging technology, it consists of cylindrical sensors that can be installed as close as 18 mm to the interaction point.
In order to validate the technology, test chips were produced in a first submission named MLR1....
The CROC-V1 readout front-end (FE) chip was designed by the RD53 collaboration for the CMS Phase-2 Inner Tracker Upgrade. It is designed to cope with the extreme radiation and hit rates of the HL-LHC and it is based on the 65 nm CMOS technology and a novel analog FE design featuring linear charge to Time-over-Threshold (ToT) conversion. In this contribution, the characterization measurements...
To cope with an increase of luminosity at Run-3 of the LHC, a new trigger readout path has been installed to the Liquid Argon Calorimeters.
More than 1500 boards of the legacy system were refurbished and re-installed, 124 new on-detector boards equipped with large FPGAs were added to digitize the calorimeter trigger signals, and all the monitoring and control infrastructure is being adapted...
A high-speed, low-power analog front end (AFE) utilizing a current-mode signal path has been designed for 4D tracking applications where precision time resolution of order 50 ps is a requirement. The preamplifier concept is based on a prior art current-feedback CMOS topology [1]. The power consumption of the AFE is 6 uA at 0.9 V process voltage. An on-chip test bench comprised of a variable...
Three new Point-of-Load (POL) converters, suitable for the High Luminosity – Large Hadron Collider (HL-LHC) experiments and for space/avionic applications, are under development. The two DCDC converters, called bPOL48V and rPOL48V, allow a significant improvement in the power delivery requirements as they can provide higher power at an increased input voltage of 48V, compared to existing...
To cope with the challenges posed by the High-Luminosity LHC, the CMS experiment will feature a new silicon tracker. The modules for the inner tracker are hybrid silicon pixel modules based on a new readout ASIC, developed by the RD53 Collaboration, capable of sustaining higher hit rates and radiation levels and enabling the use of serial-powering chains. The qualification of the latest...
The CMS tracker phase-2 upgrade modules are required to reach noise levels close to the ones expected from the analog front-end attached to an ideal pixel/strip. Module prototypes, featuring the latest and final prototype hybrids before the production, showed noise that was higher than the expected which could pose a problem in terms of achieving the hit efficiency target. Investigations that...
The Belle II experiment relies on a level-1 trigger system to reduce background and preselect events of interest for particle physics. The Central Drift Chamber is the main track detector which makes its trigger system important for online track reconstruction. To improve its hit efficiency a new extension of the track segment finder for low angel tracks is designed. By combining hardware and...
The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65nm ISC process in the framework of the CERN-EP R\&D on monolithic sensors and the ALICE ITS3 upgrade.
It features a 32x32 binary pixel matrix at 15 $\mu m$ pitch with event-driven readout, based on GHz range time-encoded digital signals including Time-Over-Threshold....
Latency and computational resources are key constraints for high bandwidth, low latency trigger systems. In these systems, even if a GPU/FPGA is used to accelerate computation, transferring data between components is still a costly operation for the host. In this work, we study a computational storage system employing FPGAs to detect supernova neutrino bursts, with a particular focus on LArTPC...
ASICs designed for HEP embed always more digital components and require complex and critical verifications. Prototyping enables implementations of digital part of ASIC in programmable components such as FPGA. Interactions with external devices such as DAQ, micro-controller or other FPGA are then possible. Debugging of internal firmware or complex stimuli becomes easier and faster than...
This paper presents 4-channel readout electronics for small-diameter Muon-Drift-Tube (sMDT) detectors. Design is optimized largely for higher detection rate of events at High Luminosity of LHC and thus significantly reducing the impact of pile-up events and eliminating use of long deadtime logic. Analog chain of the design consists of Charge-Sensitive-Preamplifier, to convert input charge into...
The Front-End Link eXchange (FELIX) system is a new ATLAS DAQ component designed to meet the evolving needs of detector readout into the High-Luminosity LHC era. FELIX acts as the interface between the data acquisition; detector and trigger timing and systems; and new or updated trigger and detector front-end electronics. FELIX routes data between custom serial links from front-end electronics...
The planned MALTA3 DMAPS designed in the standard TowerJazz 180 nm Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x1015 MeV neq/cm2. The effectiveness of these changes have been demonstrated in recent measurements with a small-scale mini-MALTA demonstrator chip. Proposed...
Recurrent dielectric breakdowns on the cryogenics instrumentation during the CERN LHC Electrical Quality Assurance (ELQA) campaigns led to an investigation of their root causes. During the CERN Long Shutdown 2 (LS2), several weaknesses were identified like floating wires or cable screens, cabling non-conformities, connector assembly issues, and weakness of the electronic conditioning cards....
For the CMS tracker Phase-2 upgrade new modules with silicon strip sensors are being developed. Each module features a Service Hybrid (SEH) responsible for communication with the tracker back-end and power distribution to the module components. Here, a two stage DC-DC conversion scheme is used for the supply of low voltage. For modules using the latest generation of SEHs an increase in module...
Single photon sensitive detectors used in high energy physics are required to cover very large areas, with a strong demand for an ever finer imaging capability. We are evaluating the LAPPD as a possible candidate for future Cherenkov ring imaging detectors, performing tests on a generation I device, which is capacitively coupled to a custom designed anode back plane, consisting of various...
To increase granularity, resolution, and provide longitudinal shower shape information from the ATLAS LAr calorimeters to its level-1 trigger processor, a new radiation-hard board has been designed during the phase-1 upgrade. This Lar Trigger Digitizer Board adapts and digitizes up to 320 detector inputs using custom ADCs and sends the serialized data through 200Gbps optical links. The run...
The operation of CMS at the HL-LHC requires an upgrade of the readout electronics. These new modern micro-electronics require power at precise voltages between 1.2V and 2.5V. We will deliver this power using a 3-stage system, comprising AC-DC conversion to 400VDC followed by radiation-tolerant 12V DC-DC power converters feeding radiation-hard point-of-load DC-DC converter. We have studied an...
Abstract:
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs of voltages or temperatures to an lpGBT ADC channel through a 6-bit decoder. A total of 92x3 dies were fabricated in two batches by the TSMC 130 nm CMOS technology. All of them passed the quality...
The high-luminosity LHC requires a complete overhaul of the ATLAS inner tracker subsystem, including a new silicon-strip charged-particle tracking detector. The HCCStar (Hybrid Controller Chip) is one of three new ASICs for this subsystem. As the interface to multiple binary readout ASICs for the strip detector, the HCCStar buffers and forwards controls signals and trigger and readout requests...
PASTTREC is an 8-channel readout ASIC for the Straw Tube Tracker (STT) and the Forward Tracker (FT) detectors in the PANDA and for the Straw Tracking System (STS) in the HADES experiments, both at the FAIR facility. Since more than 1500 ASICs were produced for both experiments, efficient qualification tests are required. For this purpose, the multi-chip test setup and dedicated verification...
The new electronics of the ATLAS TileCal for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and and mitigates and radiation damage by means of a double-redundant scheme,...
The ITk Strip is a silicon-strip charged-particle detector that is going to be installed in the ATLAS experiment for the HL-LHC. GaNFETs are radiation-tolerant transistors that permit switching off high voltage to malfunctioning sensors. To ensure the reliability of the GaNFETs in the high radiation environment expected for the ITk Strip, a sample of the transistors were exposed to gamma and...
In order to achieve tens-of-ps particles time-tagging performance required at HL-LHC, the CMS clock tree is being upgraded. A radiation-hard fan-out ASIC, named RAFAEL, was developed to distribute the clock and the data to the frontend ASICs of the CMS detectors that require precision timing, including BTL and HGCAL. Its main constraint is a low additive jitter, less than 4 ps RMS, even after...
For readout electronics capable of exploiting the characteristics of 4H−SiC, we are in testing and optimization phase of a single channel circuit to continuously detect single particles up to GHz rates, including statistical pile-up detection by ToT measurements of shaped pulse signals.
Furthermore, we are evaluating an IC with 128 input channels, originally intended for X-ray imaging, which...
RISC-V is an open standard instruction set architecture with a large community that gives access to many resources (such as architecture, operating systems, tool chains, ...). The use of such a processor could be interesting in several ways for the HEP community. For example, it could be used to have a versatile supervisor of complex chips. The purpose of this presentation is to evaluate the...
The Monitoring of Pixel System (MOPSv2) chip is an Application Specific Integrated Circuit (ASIC) foreseen to provide the temperature and the voltage monitoring data of individual front-end detector modules to the Detector Control System (DCS) of the ATLAS ITk Detector.The chip is required to be radiation hard up to an ionizing dose of 500 Mrad, immune to Single Event Upsets (SEUs) and work...
Single Event Upsets (SEUs) represent a major challenge for digital electronics operated in a radiation environment.
Triple Modular Redundancy (TMR) is one of the most popular approaches to increase digital electronics resilience to SEUs.
Simulation is the most used approach for verifying the correct triplication of the designs.
This contribution describes a novel approach for verifying the...
The ATLAS level-0 barrel muon trigger for High-Luminosity LHC will use data from RPC and MDT muon detectors and from the Tile Calorimeter. RPC hit data will be collected by on-detector Data Transmitter and Collector (DCT) boards and will be sent off-detector to the Sector Logic (SL) boards. Within a latency of 390 ns the SL boards should provide muon pre-candidates to the MDT trigger processor...
Currently microprocessors are precluded from the use in several high-energy physics applications due to the harsh radiation present. The STRV-R1 (SEU-tolerant-RISC-V) RSIC-V microprocessor aims to overcome this limitation and replace the custom digital control logic found in current ASICs. A triple modular redundancy (TMR) based protection scheme is applied to protect the RISC-V microprocessor...
During the ATLAS phase II upgrade, the tracking system of the ATLAS exper-
iment will be replaced by an all-silicon detector called the ITk (Inner Tracker)
with a pixel detector as the most inner part.
The control and monitoring data of the new system will be aggregated from an
on-detector ASIC called MOPS (Monitoring Of Pixel System) and sent to the
DCS using a new interface called...
In order to validate the design of the new all-silicon Inner Tracker (ITk) for ATLAS for the HL-LHC, a series of system tests has been performed, to assess the performance of prototype planar and 3D pixel modules arranged into serial power chains mounted on to realistic mechanical structures. In this report, the prototype loaded local supports and test infrastructure is described and the key...
A new silicon-strip charged-particle detector (ITk Strip) is a major subdetector of the future upgrade of the ATLAS experiment for the HL-LHC. The HCC and AMAC chip are radiation-tolerant ASICs that contribute to the front-end readout, monitoring and control of the ITk Strip subdetector. Comprehensive probe station testing procedures have been developed to guarantee the reliability of each...
The LHCb Experiment was upgraded to a trigger-less system reading out the full detector at 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator (VELO) is a hybrid pixel detector read out by the "VeloPix" ASIC with on-chip zero-suppression. This talk describes a novel way of calibrating the VELO detector based on a dedicated firmware, implemented...
The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. In this work we present the...
The Zero Degree Calorimeters were designed to provide the measurement of the event geometry and the luminosity in heavy ion operation. The readout system was redesigned in order to operate in continuous mode without dead time at 5 MHz event rate. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of about 1 GSps, assembled on an FPGA Mezzanine Card. The...
After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs...
As high readout channel density and compact design become the norm for HEP detectors so is operation at temperatures below the experimental site dewpoint. This increases the importance of humidity and temperature monitoring systems that are also adapted to the detector environment. In what follows we describe the systems we developed targeting compactness, cost and integration to our DCS/DSS...
Silicon Photonics is a promising technology for future HEP experiments and upgrades. Such experiments and upgrades will require high levels of radiation tolerance and Silicon Photonics Modulators have already been shown to be very radiation tolerant when exposed to high levels of TID under certain conditions. We demonstrate for the first time that changing the temperature of Ring Modulators...
Synchronizing the different parts of a Particle Physics detector is an essential part of its operation. In the DUNE liquid argon neutrino detector timing information is transmitted to the readout systems and time-stamped data is sent to the DAQ.
We describe the DUNE timing system, which uses Duty Cycle Shift Keying with 8b10b encoding and a simple message protocol. The system is designed to...
