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Summary
With the installation of LHC and its associated experiments approaching completion, CERN and its collaborating institutes are now considering an upgrade of the accelerator to achieve higher beam luminosity, the SLHC. Higher luminosity will bring the benefit of improving the statistical accuracy of the measurements but, it will also impose more stringent requirements on the performance of the data acquisition systems as well as on their radiation tolerant characteristics. Some of the systems and their components will have thus to be redesigned to cope with higher data rates and higher radiation levels. In particular the data transmission links will have to be upgraded to wider bandwidths in order to cope with the larger amounts of physics data being produced by the detectors. To increase the bandwidth without paying a penalty on the detector’s mass budget it is necessary to use fewer optical links at higher data rates rather than simply increasing the number of links. The GBT ASIC architecture was developed under this perspective. It is target at high speed (~4 Gbps) data transmission between the detectors and the counting room and it aims at providing simultaneous transmission of physics, trigger and experiment control data over the same link. The GBT will act thus simultaneously as a data-link and as a TTC transmitter and receiver incorporating many of the functions that traditionally have been separated physically and functionally in data-acquisition, timing, trigger and slow control links. The GBT will implement point-to-point duplex links allowing bidirectional data transmission between the counting room and the detectors.
In other to simplify the development and maintenance of the links the GBT interface will adopt commercial standards like the Gbit-Ethernet. Moreover, the communications protocol to be adopted is constrained so that it will be possible to develop compatible firmware in most standard FPGAs existing today in the market.
Due to the beam luminosity increase, the total dose radiation levels that the on detector electronics will be exposed to are expected to increase in the same proportion reaching the 100 Mrad level for some of the inner detectors. These high levels of radiation will pose long term reliability problems due to total dose effects which can be minimized by using advanced CMOS commercial technologies and following special layout techniques previously developed for the LHC ASICs. The GBT IC will be thus fabricated in a commercial 130 nm technology which will ensure the required radiation tolerance as well as the capability to implement large bandwidth transmission circuits (~4 Gbps). The higher luminosity will also be linked to an increase of the Single Event Upset rates. SEUs are a major impairment to error free data transmission at high data rates. To deal with this situation the GBT adopts a robust error correction scheme that will allow to correct burst of errors cased by SEUs.
The paper will describe in detail the proposed architecture, the communications protocol and the forward error correction code used. The paper will also discuss some of the GBT circuits and in particular will describe the techniques used to deal with SEU in the high speed circuitry as well as the de-serializer and clock recovery circuits.
