Speaker
Description
Summary 500 words
Power cycling is a crucial technique to realize the low-mass detectors of the future linear colliders ILC or CLIC. The basic concept implies shutting down a substantial fraction of the on-detector front-end electronics during the gaps between the bunch trains. For ILC the bunches trains are 1 ms long with 199 ms of idle time and for CLIC 200 ns with a idle time of 20 ms. Thus, in principle, average power could be a factor of 100 or so less than peak power with huge benefits for the physical reach of the experiments.
The realization of power cycling is not entirely straightforward. It is not practicable to shut-down the voltage of the electronics for various reasons, for one because the contents of the digital registers and settings would be lost. On the other hand, switching large supply currents over long cables with significant inductance in short time is problematic as well.
An effective solution is to provide a small DC current from the power supply to the detector followed by a regulator and a capacitor bank: the regulator decouples the main power line from the subsystem modules and the capacitor is a local storage of energy, active during the power-on time.
In this talk, first the principle challenges of power pulsing will be described and illustrated with examples. The challenges include the electromagnetic interference effects, Lorentz forces on cables on PCBs, induced vibration of wire bonds, radiation effects and much more. Then the requirements of a representative pixel and calorimeter will be discussed. Finally, a possible implementation of power pulsing will be described based on a model simulation with emphasis on system aspects.
