Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

Radiation Tolerance of Readout Electronics for Belle II

Sep 29, 2011, 11:50 AM
Rom EI 7 (Vienna, Austria)

Rom EI 7

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria


Dr Takeo Higuchi (KEK)


Readout and digitization electronics of upgraded B-factory detector Belle II will be located at the detector side to reduce number of analog cables. The digitized signals are transmitted out over optical serial links. The on-detector electronics is expected to suffer about 10¹² neutrons per year with kinetic energy peaking around 5 MeV. In our studies bombarding a prototype on-detector electronics equipped with FPGAs and optical transceivers at a test beam line and a nuclear reactor, we conclude the radiation tolerance of our on-detector electronics under the expected severe radiation condition. We report our studies and conclusions.

Summary 500 words

We plan to start an upgraded B-factory SuperKEKB in Japan from 2014. In SuperKEKB, the accelerator luminosity and a number of Belle II detector readout channels will increase up to 40 times and 3 times, respectively, than before. To accommodate with the increased readout channels, we readout and digitize the detector analog signals in or on the detector and transmit them out over optical serial links.
According to a background simulation, the on-detector electronics is expected to suffer about 10¹² neutrons per year coming from beam pipes with kinetic energy peaking around 5 MeV, which may damage the FPGAs and optical transceivers equipped on the on-detector electronics.
To verify the radiation tolerance of the on-detector electronics, we carry out beam tests bombarding a prototype on-detector electronics with neutrons. The prototype on-detector electronics is linked with a prototype far-detector electronics located in the radiation-safe room via optical fibers. The far-detector electronics transmits predefined random data array to the on-detector electronics. The on-detector electronics echoes the received data back to the far-detector electronics together with a single event upset (SEU) count happened in its FPGA. The far-detector electronics detects a fault in the on-detector electronics FPGA by transmutations in the echoed-back data and by the SEU counts. Both the on-detector and far-detector electronics equip Xilinx Virtex5 FPGA, and AVAGO or FINISAR optical transceivers.
After 5-year equivalent neutron irradiation by a tandem accelerator with neutron kinetic energy peaking around 4.36 MeV, we observe no permanent damage in the FPGAs, which is defined as damage unrecoverable even after a power cycle. As well, we observe no permanent damage in the optical transceivers after 2-year equivalent neutron irradiation.
In contrast to the permanent damage, we observe transient faults in the FPGA logics, which are defined as faults recoverable by itself or by firmware download. To determine much safer electronics design and layout against the transient faults, we bombard Xilinx Virtex5 and Spartan6 FPGAs with neutrons at a nuclear reactor with neutron kinetic energy peaking around 300 keV varying a neutron incident angle (θ = 0° and 180°). Virtex5 FPGA (flip-chip package) show double tolerance in the θ = 0° case than in the θ = 180°, while Spartan6 FPGA (wire-bonded package) show 1.4 times tolerance in the θ = 180° case than in the θ = 0°, contrary. In addition to above configurations, we irradiate Xilinx5 FPGAs by neutrons with incident angle θ = 90°, which show severest multi-bit fault rate unlike other two angles.
Finally, we compare the radiation tolerance between Virtex5 and Spartan6 FPGAs. We find the head side of Virtex5 FPGA shows 1.7 times radiation tolerance than the tail side of Spartan6 FPGA.
We conclude the readout electronics equipped with the Virtex5 FPGA for the Belle II detector will survive against 10¹² neutron irradiation per year with kinetic energy peaking at 5 MeV for at least 5-year operation. To achieve less faulty conditions in the FPGAs, we align the package head of Virtex5 FPGA to face to the beam pipe.

Primary author


Prof. Mikihiko Nakao (KEK)

Presentation materials