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Description
Summary 500 words
The current read-out electronics of the Level-1 Global Trigger of CMS is based on a VME-bus system, which consists of several FPGA VME boards mounted in a VME9U crate. The Global Trigger receives trigger objects from the Global Calorimeter Trigger and the Global Muon Trigger and applies in parallel up to 128 physics trigger requirements, so-called ‘Algorithms’. In addition, up to 64 so-called ‘Technical Trigger’ signals can be used to either accept or reject events. Each of the 128 possible algorithms applied during a given data taking period represents a complete physics trigger requirement and is monitored by a rate counter. As a last step, the Algorithms are combined by a final OR function to generate an ‘L1_Accept’ signal that starts the Data Acquisition System and the Higher Level Trigger software. All Algorithms can be prescaled to limit the overall Level-1 trigger rate. The Global Trigger group is developing and implementing the next generation (upgrade) of the Level-1 Global Trigger hardware based on MicroTCA technology.
As MicroTCA has been designed for mission critical systems and high availability, it has inherent support for live insertion and extraction of all Field Replaceable Units (FRUs). The Advanced Mezzanine Module (AMC) specification and the MicroTCA specifications define a hot-swap model for system components, which clearly defines the module’s states and the transitions between them. We will not review all the PICMG specifications in this paper but rather aim at developing a concept and implementing it as a practical future oriented system answering all requirements for Global Trigger system integration.
The main reasons for switching from VMEbus to MicroTCA are that MicroTCA has implemented an extensive remote management system that detects all possible faults on plug-in boards, in the power supply systems and in the ventilation system.
The requirements of the Global Trigger in the experiment are slightly different from those of the telecommunication applications that inspired the development of the MicroTCA specification. We would like to have the flexibility to easily modify the signal/protocols that access the fabric of the MCH (MicroTCA Carrier Hub) and the hardware that handles these. (The MCH is the central management and data-switching device in a MicroTCA system).
The next generation of the Global Trigger is designed based on the powerful Virtex-6 and Virtex-7 FPGAs, which combine unsurpassed flexibility with regard to reconfiguration and high robustness, and also benefits from the testability aspect. The Global Trigger is going to be designed for high-performance, high-bandwidth, and short-latency processing applications. The new aspects to be emphasized are: a) development and implementation of just one card type for the whole system, b) reconfigurability, allowing for more flexibility and a larger number of algorithms, c) testability and d) usability.
All I/O types of the Global Trigger will be designed and implemented with high speed serial links over optical fiber cables.
The number of the above-mentioned algorithms and the prescale factors that can be applied to them are limited in the current version of the hardware. The next generation will allow physicists to use more algorithms in a more flexible way, redefining them quickly when needed and applying any required prescale factors.
