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Description
Summary 500 words
The prototype micro TPC is composed of a pixelized anode featuring 2 orthogonal series of 256 strips of pixels (X and Y) and a micromesh grid defining the delimitation between the amplification (grid to anode) and the drift space (cathode to drift). The location of the pixels fired is obtained by using the coincidence between the x and y strips (the pixel pitch is 350 µm). Then, the coordinates in the anode plane are reconstructed by collecting primary electrons produced in the drift region. Knowing the electron drift velocity, the third dimension is obtained by sampling the anode signal every 20 ns.
After going through a first prototype phase, 16 channels ASIC equipping a 2x96 strips of pixels chamber, a new 64 channel version was developed in order to improve the characteristics (signal to noise ratio, offset correction, serial link frequency) and the integration density.
Each ASIC channel consists of a low noise charge preamplifier with two outputs (voltage and current), an auto-zero correction, a current discriminator whose threshold is fixed by a DAC (LSB~300nA). The preamplifier is based on a folded cascode structure with a large PMOS input transistor to maximize the signal to noise ratio. Due to the fact that the electronics are auto triggered the capacitor is discharged through a resistor with a decay time constant of 8μs.
The energy measurement is provided by 4 summing shaper (CR-RC3) in two different gains with a ratio of twelve. Each shaper is fed by the 16 preamplifier voltage outputs.
The current output, which is an amplified copy of the integration current flowing through the feedback capacitor, is connected to a fast current discriminator. The latter is a CMOS inverter maintained in linear mode to improve its commutation speed.
In order to match the DAC range an auto-zero correction has been added to the preamplifier output to compensate the DC offset current.
At a rate of about 1Hz the current output is disconnected from the discriminator input during 10µs and the residual offset is measured and memorized in a low leakage storage cell. During the remaining time, i.e. in normal operation, the correction is applied to the output branch via a current mirror to modify its polarisation and thus cancel the offset current.
The hit strip information, as well as the hit duration, is provided by the corresponding comparator output. In order to reduce the ASIC pin count and the power consumption, the 64 discriminator outputs are sampled at a rate of 50MHz and transferred through 8 LVDS serial links at a rate of 400MHz.
The common internal 400MHz clock is generated by a Phase Locked Loop synchronized with a 50MHz reference clock.
Eight ASIC were tested and validated on a 2x256 strips of pixels prototype. Results will be presented.
