Conveners
A1b - ASICs
- Alessandro Marchioro (CERN)
Mark Raymond
(Imperial College London)
27/09/2011, 11:00
ASICs
Oral
A 130 nm CMOS chip has been designed for silicon microstrip readout at the SLHC. The CBC has 128 channels, and utilises a binary un-sparsified architecture for chip and system simplicity. It is designed to read out signals of either polarity from short strips (capacitances up to ~ 10 pF) and can sink or source sensor leakage currents up to 1 microamp. Details of the design and measured...
Dr
Hubert Kroha
(Max-Planck-Institut fuer Physik, Munich)
27/09/2011, 11:25
ASICs
Oral
We discuss the development and performance of a new analogue and digital readout chip for the Monitored Drift-Tube (MDT) chambers of the ATLAS muon spectrometer using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip was designed to match the analogue performance of the presently used device in 0.5 micron Agilent technology which is now obsolete....
Dr
Matteo Beretta
(Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)
27/09/2011, 11:50
ASICs
Oral
We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments.
We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and...
Mr
Eduardo Picatoste Olloqui
(Universidad de Barcelona)
27/09/2011, 12:15
ASICs
Oral
An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. The circuit is based on a two fully differential interleaved channel with a first amplifier stage and a switched integrator. It offers an electronically cooled input termination at the input to achieve the stringent noise requirements. Compared to previous designs, its novelty relies in the use of...
