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TWEPP 2011 Topical Workshop on Electronics for Particle Physics

26–30 Sept 2011
Vienna, Austria
Europe/Zurich timezone

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Session

A1b - ASICs

A1b
27 Sept 2011, 11:00
Vienna, Austria

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria

Conveners

A1b - ASICs

  • Alessandro Marchioro (CERN)

Presentation materials

There are no materials yet.

  1. 12. The CMS Binary Chip for microstrip tracker readout at the SLHC
    Mark Raymond (Imperial College London)
    27/09/2011, 11:00
    ASICs
    Oral
    A 130 nm CMOS chip has been designed for silicon microstrip readout at the SLHC. The CBC has 128 channels, and utilises a binary un-sparsified architecture for chip and system simplicity. It is designed to read out signals of either polarity from short strips (capacitances up to ~ 10 pF) and can sink or source sensor leakage currents up to 1 microamp. Details of the design and measured...
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  2. 46. Development of a new Preamplifier-Shaper-Discriminator Chip for the ATLAS Muon Drift Tube Chambers in 130 nm IBM Technology
    Dr Hubert Kroha (Max-Planck-Institut fuer Physik, Munich)
    27/09/2011, 11:25
    ASICs
    Oral
    We discuss the development and performance of a new analogue and digital readout chip for the Monitored Drift-Tube (MDT) chambers of the ATLAS muon spectrometer using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip was designed to match the analogue performance of the presently used device in 0.5 micron Agilent technology which is now obsolete....
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  3. 94. Associative Memory design for the Fast TracKer processor (FTK) at ATLAS
    Dr Matteo Beretta (Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)
    27/09/2011, 11:50
    ASICs
    Oral
    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and...
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  4. 96. Low Noise Front End ASIC with Current Mode Active Cooled Termination for the Upgrade of the LHCb Calorimeter
    Mr Eduardo Picatoste Olloqui (Universidad de Barcelona)
    27/09/2011, 12:15
    ASICs
    Oral
    An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. The circuit is based on a two fully differential interleaved channel with a first amplifier stage and a switched integrator. It offers an electronically cooled input termination at the input to achieve the stringent noise requirements. Compared to previous designs, its novelty relies in the use of...
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