A2 - ASICs
- Christophe de La Taille (CNRS LAL Orsay)
Mr Jakub Moron (AGH University of Science and Technology)
9/27/11, 2:50 PM
The design and measurements results of low power Phase-Locked Loop (PLL) prototype for applications in particle physics detectors readout systems are presented. The PLL is designed and fabricated in 0.35~$\mu$m CMOS technology. First measurements show that the ASIC is fully functional and generates clock in the frequency range 380MHz-1.1GHz. The PLL power consumption at 1~GHz is about 4.5...
Ms Nathalie SEGUIN-MOREAU (OMEGA / IN2P3 - CNRS)
9/27/11, 3:15 PM
SKIROC (Silikon pin Kalorimeter Integrated ReadOut Chip) is the very front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) of the future International Linear Collider. The very fine granularity of the ILC calorimeters implies a huge number of electronics channels (82 millions) which is a new feature of “imaging”...
Dr David Gascon (Universidad de Barcelona)
9/27/11, 3:40 PM
A wideband current mode preamplifier with 16 bits dynamic range (DR) is presented. It has been designed for the cameras of the Cherenkov Telescope Array (CTA). A novel current division scheme at the very front end part of circuit splits the input current in to two scaled currents which are connected to independent current mirrors. The mirror of the high gain path comprises a saturation control...